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K. Samulewicz
K. Samulewicz
Technical University of Berlin
Electronic engineering
Materials science
Wafer
Chip-scale package
Wafer dicing
3
Papers
53
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Gold TSVs (Through Silicon Vias) for High-Frequency III-V Semiconductor Applications
2016
ECTC | Electronic Components and Technology Conference
K. Kroehnert
V. Glaw
G. Engelmann
Rafael Jordan
K. Samulewicz
K. Hauck
R. Cronin
M Robertson
O. Ehrmann
K.-D. Lang
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Citations (1)
Fab Integrated Packaging (FIP): a new concept for high reliability wafer-level chip size packaging
2000
ECTC | Electronic Components and Technology Conference
M. Topper
J. Auersperg
V. Glaw
K. Kaskoun
E. Prack
B. Keser
P. Coskina
D. Jager
D. Fetter
O. Ehrmann
K. Samulewicz
C. Meinherz
S. Fehlberg
C. Karduck
Herbert Reichl
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Citations (37)
Wafer level package using double balls
2000
APMPPI | International Symposium on Advanced Packaging Materials. Processes, Properties and Interfaces
Michael Töpper
V. Glaw
P. Coskina
J. Auersperg
K. Samulewicz
M. Lange
C. Karduck
S. Fehlberg
O. Ehrmann
Herbert Reichl
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Citations (15)
1