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J. Auersperg
J. Auersperg
Technical University of Berlin
Materials science
Chip-scale package
Electronic engineering
Chip
Engineering
3
Papers
74
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Integration of passive and active components into build-up layers
2002
EPTC | Electronics Packaging Technology Conference
A. Ostmann
A. Neumann
J. Auersperg
C. Ghahremani
G. Sommer
R. Aschenbrenner
Herbert Reichl
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Citations (22)
Fab Integrated Packaging (FIP): a new concept for high reliability wafer-level chip size packaging
2000
ECTC | Electronic Components and Technology Conference
M. Topper
J. Auersperg
V. Glaw
K. Kaskoun
E. Prack
B. Keser
P. Coskina
D. Jager
D. Fetter
O. Ehrmann
K. Samulewicz
C. Meinherz
S. Fehlberg
C. Karduck
Herbert Reichl
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Citations (37)
Wafer level package using double balls
2000
APMPPI | International Symposium on Advanced Packaging Materials. Processes, Properties and Interfaces
Michael Töpper
V. Glaw
P. Coskina
J. Auersperg
K. Samulewicz
M. Lange
C. Karduck
S. Fehlberg
O. Ehrmann
Herbert Reichl
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Citations (15)
1