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Eun Young Park
Eun Young Park
SK Hynix
Duty cycle
DDR3 SDRAM
Jitter
Electronic engineering
Real-time computing
2
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26
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A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces
2012
IEEE Journal of Solid-state Circuits
Hyun Woo Lee
Hoon Choi
Beom-Ju Shin
Kyung Hoon Kim
Kyung-Whan Kim
Jae-il Kim
Kwang-Hyun Kim
Jong Ho Jung
Jae Hwan Kim
Eun Young Park
Jong-sam Kim
Jonghwan Kim
Jin Hee Cho
Namgyu Rye
Jun Hyun Chun
Yunsaing Kim
Chulwoo Kim
Young Jung Choi
Byong Tae Chung
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A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface
2010
ISCAS | International Symposium on Circuits and Systems
Hyun Woo Lee
Yong-Hoon Kim
Won Joo Yun
Eun Young Park
Kang Youl Lee
Jae-il Kim
Kwang-Hyun Kim
Jong Ho Jung
Kyung-Whan Kim
Nam Gyu Rye
Kwan Weon Kim
Jun Hyun Chun
Chulwoo Kim
Young Jung Choi
Byong Tae Chung
Joong Sik Kih
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