Old Web
English
Sign In
Acemap
>
authorDetail
>
Suguru Warashina
Suguru Warashina
Electronic circuit
CMOS
Phase-locked loop
Electronic engineering
Optoelectronics
4
Papers
0
Citations
0
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (4)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
Advantages of Ultra-Thin SIMOX/CMOS based on Well-Established $\bf 0.8~{\mbi \mu}m$ Mass-Production Technologies for Low Power 1 V Phase Locked Loop Circuits
1996
Japanese Journal of Applied Physics
Osamu Tsuboi
Suguru Warashina
Kazuo Sukegawa
S Kawai
Seiichiro Kawamura
Shinichi Sekine
Keniji Takada
Hirokazu Suzuki
Show All
Source
Cite
Save
Citations (0)
Advantages of Ultra-Thin SIMOX/CMOS based on Well-Established 0.8 µm Mass-Production Technologies for Low Power 1 V Phase Locked Loop Circuits
1996
Japanese Journal of Applied Physics
Osamu Tsuboi
Suguru Warashina
Kazuo Sukegawa
S Kawai
Seiichiro Kawamura
Shinichi Sekine
Keniji Takada
Hirokazu Suzuki
Show All
Source
Cite
Save
Citations (0)
Advantages of Ultra-Thin SIMOX/CMOS Based on Well-Established 0.8μm Mass-Production Technologies for Low Power 1V PLL Circuits
1995
The Japan Society of Applied Physics
Osamu Tsuboi
Suguru Warashina
Kazuo Sukegawa
S Kawai
Seiichiro Kawamura
Shinichi Sekine
Keniji Takada
Yasuo Suzuki
Show All
Source
Cite
Save
Citations (0)
Scaling Merits of Ultra Thin Film SOI/CMOSFET's for Low Power Dissipation
1994
The Japan Society of Applied Physics
Suguru Warashina
Osamu Tsuboi
Kazuo Sukegawa
N. Sato
Show All
Source
Cite
Save
Citations (0)
1