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Yukio Nishida

Renesas Electronics

45

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Si:C-S/D Engineering using Cascade C 7 H x Implantation Followed by Rapid Solid-Phase Epitaxy and Laser Annealing for nMOSFET with Highly-Strained and Low-Resistive S/D

2013 The Japan Society of Applied Physics
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Temperature Coefficient of Threshold Voltage in Metal/High-k Gate Transistors with Various Thickness of TiN and Capping Layers

2009 The Japan Society of Applied Physics
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Gate Leakage Advantage of LaO Incorporation for V t Tuning in High-k nMOSFETs over Metal Gate WF Control

2009 The Japan Society of Applied Physics
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Low-Temperature Silicon Oxide Offset Spacer using Plasma Enhanced Atomic Layer Deposition for High-k/Metal Gate Transistor

2009 The Japan Society of Applied Physics
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Thin-Metal Inserted Single-phase Ni-FUSI(MISF) and High-k Gate Stack for Productive LSTP CMOS Application

2008 The Japan Society of Applied Physics
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Stress from Discontinuous SiN Liner for Fully Silicided Gate Process

2008 Japanese Journal of Applied Physics
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Enhanced Performance of Gate-First p-Channel Metal-Insulator-Semiconductor Field-Effect Transistors with Polycrystalline Silicon/TiN/HfSiON Stacks Fabricated by Physical Vapor Deposition Based In situ Method

2007 Japanese Journal of Applied Physics
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Reduction of Threshold Voltage by Diffusion Control Technique in p-MISFETs Using Poly-Si/TiN/HfSiON Gate Stacks

2007 IEEE Electron Device Letters
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The Impact of F and N Incorporation Technique on Advanced Gate Stacks

2007
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Local Bonding Structure of High-Stress Silicon Nitride Film Modified by UV Curing for Strained Silicon Technology beyond 45 nm Node SoC Devices

2007 Japanese Journal of Applied Physics
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Citations (13)