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Y. Hiura
Y. Hiura
Toshiba
Electronic engineering
Optoelectronics
Physics
CMOS
EPROM
5
Papers
124
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Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyond
1998
IEDM | International Electron Devices Meeting
Y. Hiura
A. Azuma
Kazuaki Nakajima
Yasushi Akasaka
Kiyotaka Miyano
H. Nitta
A. Honjo
Kenji Tsuchida
Y. Toyoshima
Kyoichi Suguro
Yusuke Kohyama
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A 3.3 V-only 16 Mb flash memory with row-decoding scheme
1996
ISSCC | International Solid-State Circuits Conference
Shigeru Atsumi
Akira Umezawa
Masao Kuriyama
Hironori Banba
Nobuaki Ohtsuka
Naoto Tomita
Y. Iyama
Takeshi Miyaba
R. Sudoh
Eiji Kamiya
Masao Tanimoto
Y. Hiura
Yoshiko Araki
Eiji Sakagami
N. Arai
S. Mori
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A novel 0.15 /spl mu/m CMOS technology using W/WNx/polysilicon gate electrode and Ti silicided source/drain diffusions
1996
IEDM | International Electron Devices Meeting
Mariko Takagi
K. Miyashita
H Koyama
Kazuaki Nakajima
Kiyotaka Miyano
Yasushi Akasaka
Y. Hiura
Satoshi Inaba
A. Azuma
H. Koike
H. Yoshimura
Kyoichi Suguro
H. Ishiuchi
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Citations (5)
A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation
1994
IEEE Journal of Solid-state Circuits
Shigeru Atsumi
Masao Kuriyama
Akira Umezawa
Hironori Banba
Kiyomi Naruke
Seiji Yamada
Yoichi Ohshima
Masamitsu Oshikiri
Y. Hiura
T. Yamane
Kuniyoshi Yoshikawa
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Citations (38)
Degradation mechanism of flash EEPROM programming after program/erase cycles
1993
IEDM | International Electron Devices Meeting
Seiji Yamada
Y. Hiura
T. Yamane
Kazumi Amemiya
Yoichi Ohshima
Kuniyoshi Yoshikawa
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Citations (67)
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