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Biju Parameshwaran
Biju Parameshwaran
SUSS MicroTec
Materials science
Electronic engineering
Wafer
Logic gate
Transistor
2
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5
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Impact of 3D Via Middle TSV Process on 20nm Wafer Level FEOL and BEOL Reliability
2016
ECTC | Electronic Components and Technology Conference
C. S. Premachandran
Luke England
Sukeshwar Kannan
R. Ranjan
Kong Boon Yeap
Walter Teo
S. Cimino
Tan Jing
Haojun Zhang
Daniel Smith
Patrick Justison
Biju Parameshwaran
Natarajan Mahadeva Iyer
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Impact of wafer thinning on High-K Metal Gate 20nm devices
2013
ECTC | Electronic Components and Technology Conference
Adam Beece
Rahul Agarwal
Sandhya Chandrashekhar
Jagar Singh
Siddhartha Siddhartha
Ramakanth Alapati
Biju Parameshwaran
Jeff Dumas
Tyson Alvanos
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Citations (2)
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