Impact of 3D Via Middle TSV Process on 20nm Wafer Level FEOL and BEOL Reliability

The impact of wafer level reliability of TSV has been studied with respect to FEOL (Front End of Line) and BEOL (Back End of Line) reliability aspects. A TSV keep out zone (KOZ) study has been done with varying gate length and width of transistor. Gate voltage (Vg) vs saturation current (Idsat) plots show that there is negligible impact on Idsat due to mechanical stress of the TSV for