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N.G. Malur
N.G. Malur
Computer science
Microprocessor
Cache
Embedded system
Very long instruction word
3
Papers
64
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Implementation of a 4/sup th/-generation 1.8GHz dual-core SPARC V9 microprocessor
2005
ISSCC | International Solid-State Circuits Conference
Jason M. Hart
Kyung T. Lee
D. Chen
Lik Cheng
C. Chou
Anand Dixit
D. Greenley
G. Gruber
K. Ho
J. Hsu
N.G. Malur
J. Wu
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Citations (38)
First-generation MAJC dual microprocessor
2001
ISSCC | International Solid-State Circuits Conference
A. Kowalczyk
V. Adler
C. Amir
F Chiu
Choon Chug
W.J. de Lange
S. Dubler
Yuefei Ge
S. Ghosh
Tan Hoang
Rong Hu
Baoqing Huang
S. Kant
Y.-S. Kao
Cong Khieu
Suresh Kumar
Chung Lau
Lan Lee
A. Liebermensch
Xin Liu
N.G. Malur
Hiep P. Ngo
Sung-Hun Oh
I. Orginos
D Pini
L. Shih
B. Sur
Allan Tzeng
D. Vo
S. Zambare
Jin Zong
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Citations (12)
The first MAJC microprocessor: a dual CPU system-on-a-chip
2001
IEEE Journal of Solid-state Circuits
A. Kowalczyk
V. Adler
C. Amir
F Chiu
Choon Ping Chng
W.J. de Lange
Yuefei Ge
S. Ghosh
Tan Canh Hoang
Baoqing Huang
S. Kant
Y.-S. Kao
Cong Khieu
Suresh Kumar
Lan Lee
A. Liebermensch
Xin Liu
N.G. Malur
A.A. Martin
Hiep P. Ngo
Sung-Hun Oh
I. Orginos
L. Shih
B. Sur
Marc Tremblay
Allan Tzeng
D. Vo
S. Zambere
Jin Zong
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Citations (14)
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