Implementation of a 4/sup th/-generation 1.8GHz dual-core SPARC V9 microprocessor

This fourth-generation processor combines two enhanced third-generation cores using an advanced 90-nm dual-Vt, dual-gate-oxide technology. Hardware additions feature expanded caches and inclusion of a 2-MB Level-2 cache and a Level-3 tag. Layout was completely redrawn to optimize the design for manufacturability and performance in the latest technology. Special emphasis was placed on library development to improve automation and assist in custom design. The memory design methodologies were completely updated to make quality design simpler and more robust. The chip operates at 1.8 GHz while dissipating 90 W of power at 1.1 V.