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Y. J. Chang
Y. J. Chang
National Chiao Tung University
Electronic engineering
Materials science
Wafer
Interconnection
Wafer-level packaging
4
Papers
19
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Electrical performances and quality investigations of integrated bonded structures and TSVs for 3D interconnects
2012
IITC | International Interconnect Technology Conference
Kuan-Neng Chen
Y. J. Chang
C. T. Ko
S. Y. Hsu
Hung-Ming Chen
C. Hsiao
Ting-Yang Yu
Yu-Hua Chen
Wei-Chung Lo
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Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding
2012
ECTC | Electronic Components and Technology Conference
Cheng-Ta Ko
Zhi-Cheng Hsiao
Y. J. Chang
Peng-Shu Chen
Jui-Hsiung Huang
Huan-Chun Fu
Yu-Jiau Huang
C. W. Chiang
Chiung-I Lee
H. H. Chang
W. L. Tsai
Yun-Tien Chen
Wei-Chung Lo
Kua-Hua Chen
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Electrical characterization and reliability investigations of Cu TSVs with wafer-level Cu/Sn-BCB hybrid bonding
2012
VLSI-TSA | International Symposium on VLSI Technology, Systems, and Applications
Y. J. Chang
C. T. Ko
Zhi-Cheng Hsiao
Ting-Yang Yu
Yun-Tien Chen
Wei-Chung Lo
Kua-Hua Chen
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Citations (2)
Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies
2012
DIC | IEEE International D Systems Integration Conference
Cheng-Ta Ko
Zhi-Cheng Hsiao
Y. J. Chang
Peng-Shu Chen
Jui-Hsiung Huang
Hsin-Chia Fu
Yu-Jiau Huang
Chia-Wen Chiang
W. L. Tsat
Yu-Hua Chen
Wei-Chung Lo
Kuan-Neng Chen
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Citations (11)
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