Power Optimized VLSI Architecture of Distributed Arithmetic Based Block LMS Adaptive Filter
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In this paper, we are presenting a power-efficient Distributed Arithmetic (DA) based Block Least Mean Square (BLMS) Adaptive Digital Filter (ADF). The proposed DA BLMS architecture proposes a shared area-efficient Multiplier Accumulate Block that calculates both the partial filter products and the weight increment terms in the same module. It also uses Multiplexers (MUX) and Demultiplexers (DEMUX) which passes only L out of N inputs, where N and L are the filter length and chosen block size respectively, into the MAC thus helping in achieving the DA functionality along with reduced power consumption. Also, efficient truncation of the obtained error and weight update terms is performed by being able to select the non-zero-bit part of the signal to be fed back. The entire architecture is driven by a single slow clock which reduces the power consumption of the device further. On comparing with the best existing DA BLMS Structures, the proposed architecture uses 15% lesser power, 14% lesser EPS according to ASIC Synthesis, and for a filter length of N=16 and a block size of L=4 respectively.Keywords:
Application-specific integrated circuit
Completely pipelined inner product architectures are presented for FIR filtering and linear transformation. The designs use only full adders, organized to form multipliers. By cascading these multiplier structures, no additional area or time is needed to sum their products. The merits of the FFT are briefly reconsidered in the context of high throughput VLSI structures for digital signal processing.
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A partial product generator based multiplier is used to reduce the complexity of multiplication operation. This multiplier, designed using decoders and and-or cells in earlier work are modified with a multiplexer to improve the speed and area of the architecture. When approximate multipliers are employed, the complexity can be further reduced and they can be used for highly data intensive processing applications like image restoration, pattern classification etc., where an approximate operation is enough in most of the cases. A delayed least mean squared (LMS) adaptive filter is designed using Xilinx ISE and implemented in Spartan-6 development board, which itself contains an FIR filter, and modified using multiplexer and approximate compressor type adder (ACA) combination. For the FIR filter part alone, the percentage decrease in maximum path delay is 40 % and that in total area is 37%. For the delayed least mean squared (DLMS) adaptive filter these values are 17 and 47 respectively.
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A partial product generator based multiplier is used to reduce the complexity of multiplication operation. This multiplier, designed using decoders and and-or cells in earlier work are modified with a multiplexer to improve the speed and area of the architecture. When approximate multipliers are employed, the complexity can be further reduced and they can be used for highly data intensive processing applications like image restoration, pattern classification etc., where an approximate operation is enough in most of the cases. A delayed least mean squared (LMS) adaptive filter is designed using Xilinx ISE and implemented in Spartan-6 development board, which itself contains an FIR filter, and modified using multiplexer and approximate compressor type adder (ACA) combination. For the FIR filter part alone, the percentage decrease in maximum path delay is 40 % and that in total area is 37%. For the delayed least mean squared (DLMS) adaptive filter these values are 17 and 47 respectively.
Finite impulse response
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The Kalman gain (KG) equation is the key block of the Kalman filter (KF) processing. It comprises many multipliers and adders in its VLSI implementation, which is attractive for a low-power design exploring efficient arithmetic units. This work explores approximate arithmetic units to reduce power dissipation and area in the VLSI design of the KG block, maintaining an appropriate precision level for the filter application. We employ the leading one bit-based approximate (LoBA) multiplier combined with a lower-part-or (LOA) approximate adder in the main parts of the KG architecture. Our results highlight an approximate KG architecture with a decrease in power dissipation of 20.66% (1.26 times), compared with the exact one, achieving 84.85% success in identifying systems.
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VLSI-oriented multiple-valued current-mode MOS arithmetic circuits using radix-2 signed-digit number representations are proposed. A prototype adder chip is implemented with 10- mu m CMOS technology to confirm the principle of operation. A multiplication scheme using four-input current-mode wired summations for realizing a high-speed small-size multiplier is presented. The 32*32-b multiplier is composed of 18800 transistors and required fewer interconnections. The multiply time is estimated to be 45 ns by SPICE simulation in 2- mu m CMOS technology. It is shown that the technology is also potentially effective for the reduction of the data-bus area in VLSI.< >
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This paper project an competent vedic multiplier design using adders with multiplexer structure. To obtain faster results and optimized circuit design, Vedic multiplier is used. Multiplier determines the throughput in arithmetic operations and performance faster in many of the real time applications. Vedic Multiplier is a kind of low power and fast multipliers. Vedic multiplier by means of urdhva tiryagbhyam sutra is designed for 8-bit numbers. Here for performance analysis delay and power of a multiplier are considered. To get an effective output, we have replaced the ripple carry adder with multiplexer as an substitute instead of traditional ripple carry adder. By using this customized adder, it is possible to achieve minimum gate delay with reduced power consumption. Instead of using conventional carry save adder it is replaced with carry save adder using multiplexer in order to obtain output with high efficiency. By considering both ripple carry adder and carry save adder the speed and power parameters are compared. In Vedic Mathematics there are 16 Sutras, in which 2 Sutras namely Urdhva Tiryagbhyam Sutra and Nikhilam Sutra have been considered for the purpose of doing multiplication process for two 8-bit numbers. In this two 8-bit multiplication process, we have implemented Urdhva Triyagbhyam Sutra which is of vertical and crosswise.
Serial binary adder
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Over the last decades, designing reversible arithmetic circuits is one of the interesting research areas because of its ability to reduce power consumption in the circuits. This paper proposes two new design approaches of reversible binary-coded decimal (BCD) multiplier. The realization of such BCD multiplier has been achieved through binary multipliers, multiplexers, and a binary-to-BCD converter. Four types of multiplications, viz. [Formula: see text], [Formula: see text], [Formula: see text], and [Formula: see text] multiplications, have been utilized for such binary multiplication and are implemented parallelly as a combined multiplier to reduce ancilla inputs (AIs) and garbage outputs (GOs). We also propose a novel reversible BCD adder for a reversible binary-to-BCD converter with reducing AIs and GOs. The first design of the reversible BCD multiplier is integrated with the proposed BCD adder in the binary-to-BCD converter. Furthermore, the proposed reversible BCD adder is modified to reduce the AIs and the GOs, which is then integrated into the second design of the reversible BCD multiplier. The results offer appreciable reductions of AIs and GOs by at least [Formula: see text]16% and [Formula: see text]43%, respectively, compared to the existing designs found in the literature.
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This paper proposes a design method for an 8-bit multiplication with reduced delay time and lesser number of adders. Normally, two numeric data can be multiplied by repeated addition. In the case of binary multiplication, combinational circuit can be designed using manual multiplication method which requires binary addition. Carry generated because of addition affects the speed of multiplication since the present addition depends on the value of previous carry. To overcome this problem, addition with the help of multiplexer is introduced and the result is an increased speed in multiplication. Even though the proposed design is mainly for FPGA implementation, it can also be implemented in ASIC as the logical delay is reduced when compared the result in Xilinx device.
Carry (investment)
Carry-save adder
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Multiplication algorithm
Serial binary adder
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This paper presents techniques to increase the speed and improve the VLSI suitability in designing fixed-point multipliers. The implementation of high-speed multiplication algorithm using redundant binary addition tree has been investigated and a minimal logic design of Redundant Binary Signed-Digit (RBSD) adder cell is presented. The regular interconnects on structures of these adder cells result in a multiplier which is ideal for VLSI implementation. The increased speed is achieved through carry free addition of partial products using redundant signed-digit numbers. The use of multiplier recoding scheme with a group size of three, which will reduce the number of rows in the partial product matrix by a factor of three, is discussed. The complexity introduced by this recoding scheme is the need for multiples of -3 and +3 of the multiplicand which involves carry propagation free adders for these precalculation units in conventional designs. This scheme results in a significant improvement in speed and is very efficient for multipliers with large operand lengths.
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Carry-save adder
Multiplication algorithm
Residue number system
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