Minimizing Ancilla Inputs and Garbage Outputs of Reversible BCD Multiplier
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Over the last decades, designing reversible arithmetic circuits is one of the interesting research areas because of its ability to reduce power consumption in the circuits. This paper proposes two new design approaches of reversible binary-coded decimal (BCD) multiplier. The realization of such BCD multiplier has been achieved through binary multipliers, multiplexers, and a binary-to-BCD converter. Four types of multiplications, viz. [Formula: see text], [Formula: see text], [Formula: see text], and [Formula: see text] multiplications, have been utilized for such binary multiplication and are implemented parallelly as a combined multiplier to reduce ancilla inputs (AIs) and garbage outputs (GOs). We also propose a novel reversible BCD adder for a reversible binary-to-BCD converter with reducing AIs and GOs. The first design of the reversible BCD multiplier is integrated with the proposed BCD adder in the binary-to-BCD converter. Furthermore, the proposed reversible BCD adder is modified to reduce the AIs and the GOs, which is then integrated into the second design of the reversible BCD multiplier. The results offer appreciable reductions of AIs and GOs by at least [Formula: see text]16% and [Formula: see text]43%, respectively, compared to the existing designs found in the literature.Keywords:
Realization (probability)
Serial binary adder
To accelerate the adder, a new parallel integer addition algorithm — carry barrel adder algorithm was proposed. The adder applied half-adder, combining parallel and iterative feedback ideas, judging the completion of a summation according to the value of the carry chain produced after each round of iteration, which can maintain the acceleration of calculation on low power consumption. The simulation results show that the proposed design of the barrel integer adder can accelerate prominently in slight augmentation of areas.
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An adder is the basic computational circuit in digital Very Large Scale Integration design., Approximate Adders have been proposed to improve the design metrics of an adder. A multiplexer makes it possible for several input signals to share one device or resource. In this paper multiplexer based approximate full adder is proposed for low power approximate adders. The MAA architecture is build using the inverter-based multiplexer which gives high power efficiency than the other adders, for performance evaluation four types of approximate mirror adders have been referred. On analysis it is found that Multiplexer based approximate full adder is the most power efficient with a considerable propagation delay.
Carry-save adder
Serial binary adder
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Optimization techniques for decreasing the time and area of adder circuits have been extensively studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We develop the equations for single-stage parallel adder which works as a carry look-ahead adder. We also provide the design of a logarithmic stage parallel adder which can compute the carries within log2(n) time delay for n qudits. At last, we compare the designs and finally propose a hybrid adder which combines the advantages of serial and parallel adder.
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Carry-save adder
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An intelligent full adder circuit is simulated using Cadence Virtuoso Analog Design version 6.0. The complementary property between sum and carry for most of the input combination is considered for reducing the number of transistors in the full adder circuit. The parameters such as the Power consumption, Delay and Power Delay Product (PDP) are improved in the proposed CMOS full adder than the conventional CMOS full adder. The size of the chip and the number of transistors are greatly reduced with the proposed circuit. From the single bit full adder module, other parallel adder circuits such as Ripple carry Adder, Carry Look Ahead Adder, Carry Save Adder, Carry Increment adder, Carry Skip Adder, Carry Select Adder and Carry By-pass Adder are simulated. The worst-case gate delay in each case is measured and compared with other adders.
Serial binary adder
Carry-save adder
Carry (investment)
Power–delay product
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Optimization techniques for decreasing the time and area of adder circuits have been extensively studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We develop the equations for single-stage parallel adder which works as a carry look-ahead adder. We also provide the design of a logarithmic stage parallel adder which can compute the carries within log2(n) time delay for n qudits. At last, we compare the designs and finally propose a hybrid adder which combines the advantages of serial and parallel adder.
Serial binary adder
Carry-save adder
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We explain how exclusive OR and NOR circuits (XOR/XNOR) are used to realize a general full adder circuit based on pass transistors. A six-transistor CMOS XOR circuit that also produces a complementary XNOR output is introduced in the general full adder. The resulting full adder circuit is realized using only 14 MOSFETs, while having full voltage-swing in all circuit nodes. Layouts have been made in a 0.35 /spl mu/m process for both the proposed full adder circuit and another 16-transistor full adder circuit based on pass transistors. The performance of the proposed full adder is evaluated by comparison of the simulation results obtained from HSPICE for both layouts. The two adders yield similar performance in terms of power consumption, power delay product, and propagation delay. The area is somewhat lower for the proposed adder due to the reduced device count. However, due to two feedback MOSFETs in the proposed adder that need to be ratioed, there is a higher cost in terms of design effort for the proposed adder.
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XNOR gate
Power–delay product
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Full adders are discussed,and a multiplexer based full adder is designed.HSPICE simulation shows that the multiplexer based full adder consumes less power and has higher speed compared with the other adders.
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Carry-save adder
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A new adder design is proposed.Combining CLA and asynchronous self-timed techniques,the adder introduces the hybrid handshake protocol and distributes the carry-generating path with the probabilities of the carry chains.It can speed up the asynchronous adder while keeping a low power and area cost.The adder implements the 0.18μm technique of SMIC.Simulation result shows that the 32-bit asynchronous parallel adder achieves the average delay of 0.880932ns.Its speed is 7.33 times faster than the synchronous ripple adder,1.364 times faster than the asynchronous ripple adder,and 1.123 times faster than the asynchronous carry-select adder.And its area and power cost are less than those of the asynchronous carry-select adder.
Serial binary adder
Carry-save adder
Handshake
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This paper presents an efficient carry save adder design with multiplexer based adder architecture, instead of using ripple carry adder it replaces this ripple carry adder with modified adder to achieve effective output. Using this modified adder it can obtain reduced gate delay with low power consumption. The proposed design is from 8bit to 64 bit carry save adder. Where 64bit designs are most widely used in digital systems in present technology. As ripple carry adder is one of the most common type adder used in various designs, it has a long propagation delay and also consume more area and power. To reduce the gate delay and power the carry save adder is customized as i.e. carry save adder is cascaded with the ripple carry adder. In ripple carry adder first block is a half adder followed by the full adder chain and ends with a half adder. These full adders in first and second stage are replaced with modified full adder.
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Carry-save adder
Carry (investment)
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