Spin-transfer-torque magnetoresistive random-access memory (STT-MRAM) technology
Takahiro HanyuTetsuo EndohYasuo AndoShoji IkedaShunsuke FukamiH. SatoHiroaki KoikeYitao MaDaisuke SuzukiHideo Ohno
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Magnetoresistive random-access memory
Spin-transfer torque
Tunnel magnetoresistance
Non-Volatile Memory
Racetrack memory
Universal Memory
This letter presents energy-efficient MgO based magnetic tunnel junction (MTJ) bits for high-speed spin transfer torque magnetoresistive random access memory (STT-MRAM). We present experimental data illustrating the effect of device shape, area, and tunnel-barrier thickness of the MTJ on its switching voltage, thermal stability, and energy per write operation in the nanosecond switching regime. Finite-temperature micromagnetic simulations show that the write energy changes with operating temperature. The temperature sensitivity increases with increasing write pulsewidth and decreasing write voltage. We demonstrate STT-MRAM cells with switching energies of $<$
Magnetoresistive random-access memory
Tunnel magnetoresistance
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Magnetoresistive random-access memory
Spin-transfer torque
Tunnel magnetoresistance
Non-Volatile Memory
Racetrack memory
Universal Memory
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We introduce a new device for reducing the switching current, Ic, in Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM). The Double Spin-torque Magnetic Tunnel Junction (DS-MTJ) uses spin torque from both top and bottom free-layer interfaces to reduce Ic by 2x. However, unlike previous work using Double Magnetic Tunnel Junctions (DMTJs), the DS-MTJ does not suffer from reduced magneto resistance (MR) due to increased series resistance. Experimental data using 10 ns write pulses demonstrates 2x reduction in Ic, and reliable writing down to an error-floor of write-error-rate (WER) = 1e-6.
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Spin transfer torque (STT) switching‐based magnetic random access memory (MRAM) is gaining significant industrial and academic attention due to its potential application as a non‐volatile memory device in computing devices, smartphones, and so on. STT‐MRAM devices with in‐plane magnetization configuration have been marketed as niche products. Devices with out‐of‐plane magnetization are being considered for embedded memory as the first step. Aggressive goals include replacing dynamic random access memory (DRAM) with STT‐MRAM. This review article introduces the basics of STT‐MRAM and describes the recent progress in overcoming certain challenges such as reduction of power consumption and increase of storage density, which will make it a strong competitor for DRAM.
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Spin transfer torque magnetic random access memory (STT-MRAM) is recommended as one of the promising candidates for nonvolatile memory technologies. Compared with traditional memory technologies, STT-MRAM demonstrates low power consumption, fast access speed and infinite endurance, while the storage capacity reported so far has not been that large in contrast with SRAM or DRAM. Considering this, multi-level cells (MLC) based on more than one magnetic tunnel junctions (MTJ) have been proposed to further enhance the memory density.
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In this report, we presented an NV Random Access Memory cell using a novel easy and proficient model of Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ). Magnetic tunnel junction (MTJ) devices are CMOS well suited with high steadiness, high dependability and non-volatility. The combination of magnetic tunnel junction with CMOS circuits in magnetic RAM (MRAM) or Magnetic FPGA can get the digital circuits to major advantages related with non-volatile facility like immediate on/off, Zero standby power use of goods and services. MTJ (Magnetic Tunnel Junction) devices have various advantages over other magneto-resistive devices for use in MRAM cells, like MRAM produces a big signal for the read operation and a varying resistance that can make the circuit. Due to these attributes, MTJ-MRAM can operate at high velocity. A completed simulation model for the 4T and 2MTJ SRAM design is shown in this report, which is grounded on the recently confirmed STT (Spin-Transfer Torque) writing technique which promises to take down the switching current losing to ~120μA and the STT RAM cache reduces total power consumption from 13.6μW -8.2μW. This model has been confirmed in Verilog A language and the whole work carried out and ran out on cadence virtuoso platform at 45nm.
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In this work we propose a magnetic random access memory (MRAM) bit-cell design based on non-local spin transfer torque (NLSTT). In the proposed bit-cell, the data is written into the free layer of a magnetic tunnel junction (MTJ) using spin diffusion current (non-local spin injection), without injecting charge current into the tunneling oxide. Thus, the reliability issues, related to dielectric breakdown due to high tunneling current density (for high switching speed) are significantly mitigated. Separation of read and write current paths in the bit-cell helps in optimizing read and write separately. Hence, higher MgO thickness can be used for higher cell TMR and higher read disturb margin. Higher MTJ resistance resulting from thicker MgO also lets us use voltage mode sensing, that achieves higher speed for read operation. In the proposed bit-cell, we employ two supplementary spin injectors with tilted axis anisotropy, in order to compensate for the comparatively lower efficiency for non-local spin injection. Analysis of the proposed NLSTT-MRAM bit-cell is done using a physics based simulation framework, benchmarked with experimental data for lateral spin valve (LSV). Apart from high reliability, the proposed bit-cell achieves 110% higher tunnel magneto resistance (TMR) and 4X higher read margin for I ns switching speed as compared to standard I-transistor-I MTJ (1-T I-R) STT -MRAM of similar area.
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This paper presents a review and future prospects for the tunnel magnetoresistance (TMR) effect in magnetic tunnel junction (MTJ) and spin manipulation technologies such as spin-transfer torque (STT) for magnetoresistive random access memory (MRAM). Major challenges for ultrahigh-density STT-MRAM with perpendicular magnetization and novel functional devices related to MRAM are discussed.
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Spin-torque transfer magnetoresistive random-access memory (STT-MRAM) is far more energy efficient than field MRAM. This chapter describes the memory operation and the performance of STT-MRAM. It discusses energy barriers as a function of a magnetic tunnel junction (MTJ) film stack and device structure. The chapter focuses on the switching properties. The discussion starts from a simple uniform magnetization reversal model, called the Macrospin model, in which the magnetization of the entire MTJ free layer magnetization is assumed to precess in unison under spin current. Then, the chapter discusses two STT-MRAM device reliability issues: tunnel barrier degradation and data retention. It covers an MgO tunnel barrier degradation model and the relation between the thermal energy barrier and the data retention time performance at the chip level. The chapter also discusses the 1 MTJ-1 transistor MRAM cell design and scaling. It covers the SPICE model for memory chip-level circuit simulation.
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The magnetic random accessible memory (MRAM) is positioned as one of the potential candidates for future universal memory[1]. Although MRAM's endurance outperforms most of the competing technologies, MRAM has not demonstrated strong advantage on area density [2]. Furthermore, recent rapid progress on area density in competing technologies, such as, aggressive scaling on Phase Change Memory [3], multiple-level / multi-bit charge trapping flash memories [4], makes it more important to improve the MRAM array density.
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Spin-transfer torque
Non-Volatile Memory
Racetrack memory
Universal Memory
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