An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs)
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The Complementary FET (CFET) is known to be a potential device to continue the feature size scaling. However, studies forecast that increased parasitic RC neutralizes the area reduction advantage that CFETs can provide. In this paper, (1) we report that RC increase by CFETs is not that significant (only +4.25% compared to 5 track FinFET INV), and (2) propose a design methodology that optimizes the parasitics of CFET standard cells to make this happen. Our methodology shows improvements in parasitics by up to 8.15% for capacitance and 32.73% for resistance when comparing the two types of CFET structures.Keywords:
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We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-kappa/metal gate) reach their limits and physical gate length can no longer be effectively scaled down. By judiciously engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of selective device structure scaling that will enable technology scaling and contacted gate pitch scaling for several generations beyond the currently perceived limits.
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This paper presents an investigation into the parasitic capacitance of an RF contact scheme for lumped-element EAMs. Test structures are fabricated to analyse this parasitic capacitance via S11 characterisation using a vector network analyser (VNA). Optimisations of the contact scheme lead to the parasitic capacitance being reduced to <10 fF. EAMs using this contact scheme are fabricated and characterised using S11 measurements. These S11 measurements are used to simulate S21 measurements, which predict a f3dB bandwidth of near 80 GHz using an equivalent circuit model.
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The emergence of wide-bandgap power devices such as silicon carbide (SiC) MOSFETs can achieve much faster switching speeds, hence lower switching loss, than conventional silicon (Si) IGBTs. However, the faster switching speed, hence higher dv/dt can cause increased turn-on current overshoot, ringing and EMI due to the parasitic capacitance in the system. In this paper, the parasitic capacitance of a filter inductor has been analysed, where a single-layer power inductor with an EE core and rectangular conductors is used to study the factors which affect the parasitic capacitance. Methods to reduce the parasitic capacitance are proposed and analysed with the parasitic capacitance function obtained. The relationship between the parasitic capacitance and design variables such as winding pitch, thickness and dielectric constant of the insulation layer, turn-to-core distance and potting material are studied. The influence factors which can reduce the parasitic capacitance are analysed both by theoretical calculation and Finite Element Analysis (FEA). Three practical methods for reducing the parasitic capacitance are studied based on theoretical formulas. The values of the influence factors and the corresponding minimum of the parasitic capacitance are obtained by the parasitic capacitance function. The results are verified by experiment.
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This article rethinks the basic assumptions often used in analytically modeling parasitic capacitance in inductors. These assumptions are classified in two commonly-used physics-based analysis methods: the lumped capacitor network method and the energy conservation method. The lumped-capacitor network method is not the proper solution for calculating the equivalent parasitic capacitance in inductors at the first resonant frequency, but rather represents the equivalent parasitic capacitance above the last resonant frequency. The energy-conservation based method is shown to be more accurate and a reasonable solution to model the equivalent parasitic capacitance at the first resonant frequency. Multiple case studies of inductors are used for verifying the theory.
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The conventional parasitic capacitance extraction always produces bias-dependent C/sub pd/, even though from the underlying physic, the parasitic capacitance is known to be bias-independent. In this paper, an improved model is thus proposed to evaluate the parasitic capacitances of GaAs MESFET transistor from the cold-FET S-parameters measurement. The resulting C/sub pd/ is found to be independent of V/sub gs/ when V/sub gs/ < V/sub p/. In our approach, model parameters can be uniquely determined by using only two sets of cold-FET S-parameters under different Vgs biasing condition.
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The parasitic capacitances in Vertical FET(VFET) are investigated. Vertical device has additional parasitic capacitance compared with lateral device because of deeply contacted drain metal. This parasitic capacitance degrades the performance of the device. In this study, tri-gate channel VFET which eliminates the additional parasitic capacitance without broadening the device area is proposed.
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A wide-band lumped element model for a through silicon via (TSV) is proposed based on electromagnetic simulations. Closed form expressions for the TSV parasitics based on the dimensional analysis method are introduced. The proposed model enables direct extraction of the TSV resistance, self-inductance, oxide capacitance, and parasitic elements due to the finite substrate resistivity. The model's compactness and compatibility with SPICE simulations allows the fast investigation of a TSV impact on a 3-D circuit performance. The parameters' values of the proposed TSV model are fitted to the simulated S-parameters up to 10 GHz with an error less than 5%. It is shown that a TSV capacitance is highly dependent on the positions of ground contacts and has a value of tens of femto farads in a typical current technology. This value is much higher than a minimum device capacitance and requires special design methodologies such as cascaded buffers. Coupling between TSVs will be handled in another paper.
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The impact of parasitic capacitance in micron and submicron CMOS/SOS implementations is explored. Relative measures of parasitic fringing and interconnect capacitance associated with ring oscillator and high-speed 1/64 frequency divider (400 MHz at 4V) circuit layouts are investigated. Parasitic capacitance figures of merit are analyzed in terms of several key geometrical dimensions, from which sensitivity of parasitic influence on circuit speed to departure from ideal scaling laws can be deduced. Analytical and numerical results and design considerations moderating deleterious effects of parasitic capacitance in down scaling from 2 to 1 to 0.5µm CMOS/SOS technologies are discussed.
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The parasitic capacitances of a novel double-sided cooling structure of GaN power module are analyzed in this paper. Due to the additional top ceramic substrate of the structure, parasitic capacitances become more complex. By analysis, gate-source parasitic capacitance and gate-drain parasitic capacitance of all GaN devices and drain-source parasitic capacitance of upper GaN device of half bridge circuit are less than 1% of the corresponding intrinsic capacitances. However, the drain-source parasitic capacitance (14% of C oss ) of bottom GaN device of half bridge circuit increases by 30% compared with traditional single-sided cooling module, which is acceptable since the thermal resistance of this structure is about halved.
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