Research on High Performance Full Adder
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Full adders are discussed,and a multiplexer based full adder is designed.HSPICE simulation shows that the multiplexer based full adder consumes less power and has higher speed compared with the other adders.Keywords:
Serial binary adder
Carry-save adder
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Full adder is an essential component for the design and development of all types of processor. This project introduces the design of high-performance low-power full adder which acquires least area with the lowest transistor count. The high-performance low-power full adder is designed and the implementation of a 32-bit ripple carry adder based on high-performance low-power full adder circuit is described, and comparison is made with other previously designed full adders. The high-performance low-power full adder circuit is designed and the simulation has been carried out on Tanner EDA tool. The result shows that the proposed high-performance low-power full adder is an efficient full adder cell with least MOS transistor count that reduces the high power consumption and considerably increases the speed.
Serial binary adder
Carry-save adder
Transistor count
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The main building blocks used in digital signal processing and multimedia applications are the adders and multipliers. Better the performance of adder structure better will be the performance of multipliers in total aspect. Reducing power dissipation, delay and area at the circuit level is considered as one of the major factors in developing low power systems. In this we present different topologies of full adder by using CMOS technology. Performance comparison of the six different cmos full adder structures are presented in this paper those full adders are Serf full adder, 16T full adder, 14T full adder, TG-cmos full adder, static cmos full adder and TFA full adder. All these full adder structures are developed by using S-edit and T-spice of Tanner EDA tools. And the results shows that SERF full adder is constructed by using less transistor count as less as 10 transistor and also consuming less power.
Serial binary adder
Carry-save adder
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A novel full-swing, low-power and energy-aware full adder using hybrid logic scheme is presented in this paper. At first, a new energy-efficient 10T XOR-XNOR cell is designed by modifying inverter and pass transistor based 3T XOR-XNOR gates combined with a feedback loop. The performance of this new cell is compared with some reported ones and then, using this new cell and two other modules, a novel full adder circuit is proposed and evaluated in TSMC 0.18 μm CMOS process technology. Post-layout simulations using Cadence Virtuoso tool showed 33%–74% and 35%–81% improvement in terms of power consumption and power-delay product (PDP), respectively, compared with some well-known counterparts in the literature. Furthermore, high-performance claim of our proposed full adder cell is verified through the process, voltage and temperature (PVT) variations' simulation of the adders. Finally, implementation of different full adders in 4-bit ripple carry adders (RCAs) proved our new design has high performance in the aspects of power dissipation and PDP.
XNOR gate
Serial binary adder
Power–delay product
Cadence
Carry-save adder
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Adder is a critical component in arithmetic and logic units (ALUs). Minimizing the power consumption and delay of adder is an important issue. In this paper, we proposed a high performance multiplexer-based radix-4 adder with refined carry to reduce the propagation delay. To achieve high performance, the proposed radix-4 adder adopts multiplexers which are controlled by the carry signal of previous stage to avoid the long carry chain. The drivability of all outputs is strong because all outputs are full voltage swing. The proposed design was simulated by using the TSMC CMOS 45 nm technology. For 32-bit adders, compared with the previous radix-4 adder and 2-bit carry select adder, our design can reduce 16% and 19% delay, respectively; our design also achieves 13% and 66% EDP reduction, respectively.
Serial binary adder
Carry-save adder
Carry (investment)
Radix (gastropod)
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This paper presents a novel low-power and high-speed 1-bit full-adder, which is designed based on pass transistor and TG logics. The main advantage of this design is low propagation delay and lowpower consumption, which leads to achieving lower PDP than others. Intensive HSPICE simulation shows that the new full-adder consumes around 28.5% less power than 14T adder; moreover its PDPis 30% less than SS16T full- adder. We have compared two full-adders, 14T and SS16T, withour proposed full-adder. Simulation has been carried out by HSPICE in 0.18µm technology at 1.8V supply voltage.
Serial binary adder
Carry-save adder
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Full adder is an essential module in the design and development of all types of processors such as digital signal processors (DSP), microprocessors etc. Adders are the nucleus element of composite arithmetic operations like addition, multiplication, division, exponentiation etc.The various full adders available are conventional CMOS full adder, parallel prefix adders, hybrid full adders, and mirror full adders, adders using transmission gates and multiplexer logic.The main goal is to compare the existing full adder circuit's performance and to identify a Low Power Full Adder and to analyze its impact on 8-bit, 16-bit, 32-bit ripple carry adder design.Mentor Graphics IC studio tool in 180 nm technology is used to design and implement the proposed full adders and ripple carry adders.
Carry (investment)
Serial binary adder
Carry-save adder
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A novel full adder has been designed. Compared with previous architecture, the new design is better both on speed and area. At last, an example using the new full adder is given.
Serial binary adder
Carry-save adder
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This study proposes an 18-transistor full adder (FA) cell based on the full swing hybrid logic style. It has a first stage comprising the XOR-XNOR module followed by pass transistors and inverters to generate the sum and carry outputs. The performance evaluation of the proposed FA cell has been carried out using an HSPICE simulator at the 16 nm process node by comparing it with eight existing FAs over the supply voltage ranging from 0.4 to 1.0 V. The proposed adder achieved 34.77% improvement in propagation delay, 48.8% improvement in average power and 66.58% improvement in Power Delay Product compared to the conventional CMOS Mirror adder while operating at 0.8 V. Moreover, its performance metrics are also better than those of other latest existing adder cells. Hence, the proposed FA is suitable for modern high performance digital processors.
Serial binary adder
Carry-save adder
XNOR gate
Power–delay product
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This paper proposes four low power adder cells using different XOR and XNOR gate architectures. Two sets of circuit designs are presented. One implements full adders with 3 transistors (3-T) XOR and XNOR gates. The other applies Gate-Diffusion-Input (GDI) technique to full adders. Simulations are performed by using Hspice based on 180 nm CMOS technology. In comparison with Static Energy Recovery Full (SERF) adder cell module, the proposed four full adder cells demonstrate their advantages, including lower power consumption, smaller area, and higher speed.
XNOR gate
Serial binary adder
Carry-save adder
XOR gate
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In VLSI, power optimization is the main criteria for all the portable mobile applications and developments because of its impact on system performance. The performance of an adder has significant impact on overall performance of a digital system. Adiabatic logic (AL), a new emerging research domain for optimizing the power in VLSI circuits with high switching activity is discussed, in this paper, for implementing the adder circuits. Various adiabatic logic styles full adder designs are reviewed and multiplexer based hybrid full adder topology is designed and implemented with ECRL and 2PASCL AL styles. Moreover in this paper, 32 bit adders such as Ripple Carry Adder (RCA), Carry Select Adder (CSLA), Carry Save Adder (CSA), Carry Skip Adder (CSKA) and Brent Kung Adder (BKA) are realised using proposed ECRL and 2PASCL adiabatic full adders. All the adders are implemented and simulated using TANNER EDA tool 22nm technology, parameters like power, area, delay and power delay product (PDP) of all the adders are observed at different operating frequencies, with supply voltage of 0.95 v and load capacitance of 0.5 pF. The observed parameters are compared with the existing adiabatic full adder designs and concluded that the proposed adiabatic full adders have the advantages of less power, delay and transistor count. In conclusion ECRL full adder is 31% faster, has equal PDP and less area than 2PASCL full adder. At 1000MHz ECRL 32 bit carry save adder is having less delay among all the 32 bit adder and 65% less PDP than 2PASCL adder and it is concluded that ECRL 32 bit carry save adder can be selected for implementation of circuits that can be used in portable mobile applications.
Carry-save adder
Serial binary adder
Power–delay product
Transistor count
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Citations (8)