Optimization of the breakdown voltage in LDMOS transistors using internal field rings
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It is shown that field rings in the drift region of LDMOS (lateral double diffused MOS) transistors can be used to reduce the electric field at the Si/SiO/sub 2/ interface and increase the breakdown voltage of the structure. A first order analytical approach shows the upper limit of the position of the ring with respect to the channel, and the doping concentration within the ring to increase the breakdown voltage. A 2-D numerical calculation of the breakdown voltage and on-resistance of the LDMOS transistor is presented. The results, which support the analytical approach, allow the designer to use simple design rules for the implantation of high-voltage LDMOS transistors on thick epitaxial layers. A potential improvement of the breakdown voltage arises if the distance between the channel and the field ring is equal to the field plate length and the doping concentration in the ring satisfies a specified equation. Doubling the breakdown voltage is associated with a 25% increase in device area. The on-resistance depends mainly on the field ring position with respect to the channel. A good tradeoff between the breakdown voltage and on-resistance is obtained when the channel-ring distance is equal to the field plate length.< Keywords:
LDMOS
A 700 V double-resurf LDMOS (DR-LDMOS) with double-metal field plates is successfully integrated monolithically in a 1 /spl mu/ double-level metal (DLM) Bi-CMOS process for use in HV off-line switching applications. The process and device parameters, which determine the best-in-class specific on-resistance of lower than 200 mohm-cm/sup 2/, and a robust breakdown voltage of greater than 700 V, were optimized and addressed in our 1/sup st/ generation DR-LDMOS with single-level metal (SLM) process. It is found, during the DLM process development, that breakdown voltage begins to show significant degradation after stress when a 2/sup nd/ layer of dielectric layer (ILD-1) is added on top of Metal-1, as opposed to no degradation when there was no ILD-1 on top of Metal-1. This paper presents the re-optimization of DR-LDMOS with new Metal-2 field plate designs with respect to Metal-1 and ILD-1 to maintain a stable and robust breakdown voltage (BV) after stress.
LDMOS
High Voltage
Dielectric strength
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Designing of high voltage LDMOS with a reduced surface field (RESURF) structure have been investigated to achieve the optimum figure of merit, maximum breakdown voltage accompanied with low on resistance. The drift region profile and device geometry plays important role to achieve target breakdown voltage of 80V. The electrical behaviors of the designed high voltage LDMOS for both on state and off state conditions are discussed analytically in this paper.
LDMOS
Figure of Merit
High Voltage
Power MOSFET
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The optimization of the floating-ring parameters and the breakdown voltage of a lateral DMOS (LDMOS) transistor using a single floating ring is presented. A first-order analytical approach is presented, showing the upper limit of the position of the ring, with respect to the channel, and the doping concentration within the ring to increase the breakdown voltage. A 2D numerical calculation of the breakdown voltage and on-resistance of the LDMOS transistor is also presented. The results, which support the analytical approach, allow the use of simple design rules for the implementation of high-voltage LDMOS transistors on a thick epitaxial layer. It is shown that improvements of breakdown voltage is obtained if the distance between the channel and the field ring is equal to the field plate length and the doping concentration in the ring satisfies a specific relationship. With a single ring, the breakdown voltage increases from 170 to 280 V for the same device area and to over 480 V if the area is allowed to increase by 25%.< >
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Transistor model
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The breakdown voltage and on-resistance of a multi-RESURF LDMOS are studied numerically and analytically. The results are compared with those from the conventional LDMOS. Reduction of on-resistance by 23% is obtained for the multi-layer structure without degradation in the breakdown voltage. An analytical expression for the surface potential distribution of the multi-layer structure is derived which provides a useful mean to determine the breakdown voltage analytically in terms of the device parameters.
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Electric breakdown
Power MOSFET
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LDMOS
Depletion region
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This paper presents a High-k Lateral Diffused Metal Oxide Semiconductor (HK-LDMOS) with triangular trench field plate (TTFP-HK-LDMOS). The main feature of TTFP-HK-LDMOS is introducing two triangular trench field plate at both ends of the drift region. The distribution of surface electric field can be modulated by the triangular trench field plate, so that the breakdown voltage can be improved. The simulation results show that the breakdown voltage of TTFP-HK-LDMOS can reach 372V. Compare with HKLDMOS breakdown voltage, TTFP-HK-LDMOS breakdown voltage increases 28.3%. Meanwhile, the TTFP-HK-LDMOS improved figure of merits which is 2.2 times in compared with HK-LDMOS.
LDMOS
High Voltage
Power MOSFET
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It is shown that field rings in the drift region of LDMOS (lateral double diffused MOS) transistors can be used to reduce the electric field at the Si/SiO/sub 2/ interface and increase the breakdown voltage of the structure. A first order analytical approach shows the upper limit of the position of the ring with respect to the channel, and the doping concentration within the ring to increase the breakdown voltage. A 2-D numerical calculation of the breakdown voltage and on-resistance of the LDMOS transistor is presented. The results, which support the analytical approach, allow the designer to use simple design rules for the implantation of high-voltage LDMOS transistors on thick epitaxial layers. A potential improvement of the breakdown voltage arises if the distance between the channel and the field ring is equal to the field plate length and the doping concentration in the ring satisfies a specified equation. Doubling the breakdown voltage is associated with a 25% increase in device area. The on-resistance depends mainly on the field ring position with respect to the channel. A good tradeoff between the breakdown voltage and on-resistance is obtained when the channel-ring distance is equal to the field plate length.< >
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In this paper, two kinds of robust 700V DR-LDMOS (Double RESURF LDMOS) using thin epitaxial technology has been realized for level shifter and switching applications. The P-TOP layer is introduced to reduce on-resistance while maintaining high breakdown voltage for switching applications, and to increase on-breakdown voltage using JFET resistance for level shifter. The result is that the breakdown voltage of the 700V LDMOS for level shifter is 900V with on-breakdown of over 650V. In terms of switching applications, we have adopted HVPWELL layer of rainbow shape at source corner region to reduce n-type charge of N-EPI region and achieved the breakdown voltage of over 750V.
LDMOS
JFET
High Voltage
Avalanche breakdown
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A new design concept is proposed to eliminate the substrate-assisted depletion effect that significantly degrades the breakdown voltage (BV) of conventional super junction-LDMOS.The key feature of the new concept is that a partial buried layer is implemented which compensates for the charge interaction between the p-substrate and SJ region,realizing high breakdown voltage and low on-resistance.Numerical simulation results indicate that the proposed device features high breakdown voltage,low on-resistance,and reduced sensitivity to doping imbalance in the pillars.In addition,the proposed device is compatible with smart power technology.
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High Voltage
Depletion region
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