A Flash-ADC data acquisition system developed for a drift chamber array and a digital filter algorithm for signal processing
Han YiLiming LüZhao ZhangWenjing ChengWei JiY. HuangYan ZhangHongjie LiYin-Ping CuiMing LinYijie WangLimin DuanRong-Jiang HuZ. G. Xiao
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Abstract:
A Flash-ADC data acquisition (DAQ) system has been developed for the drift chamber array designed for the External-Target-Experiment at the Cooling Storage Ring at the Heavy Ion Research Facility, Lanzhou. The simplified readout electronics system has been developed using the Flash-ADC modules and the whole waveform in the sampling window is obtained, with which the time and energy information can be deduced with an offline processing. A digital filter algorithm has been developed to discriminate the noise and the useful signal. With the digital filtering process, the signal to noise ratio (SNR) is increased and a better time and energy resolution can be obtained.Keywords:
Flash ADC
SIGNAL (programming language)
Analog-to-digital converter
Serial Flash Analog to Digital Converter (ADC) is a topology which uses only N number of comparators for N bit ADC. The said converter is developed and implemented in CM OS for 6 bit resolution. The simulation results are presented for TSM C 0.35 um CM OS technology
Flash ADC
Analog-to-digital converter
Successive approximation ADC
Digital-to-analog converter
Integrating ADC
4-bit
Bit (key)
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A CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique, a flash ADC can be applied to low supply voltage. A fat tree encoder that has signal delay of O(log2 N) is used for performance. A 6-bit and an 8-bit flash ADC were designed with 0.07 mµ CMOS technology and 0.7 V power supply voltage. The 6-bit ADC operates up to 4.76 giga samples per second (GSPS) with 11.35 mW power consumption. In case of the 8-bit ADC, it consumes 48.90 mW at its high speed 3.57 GSPS.
Flash ADC
Analog-to-digital converter
Successive approximation ADC
Integrating ADC
Low-power electronics
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Flash ADC
Analog-to-digital converter
Linearity
Successive approximation ADC
12-bit
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In computerized world, The Speed, area and power are critical variables for high velocity aplplications.ADC is a mixed signal system that changes over the analog signals to the digital signals for transforming the data. In present day CMOS innovation the flash ADC is composed by utilizing the dynamic method, it fundamentally diminishes the power, voltage and delay. A flash ADC is extremely valuable for fastest speed when it is contrasted with the other ADC architectures.ADC is attempting to contrast the simple information with an arrangement of levels. In digital signal processors it is persistently challenge analog designer to enhance and grow new ADC architectures.
Flash ADC
Analog-to-digital converter
Integrating ADC
Successive approximation ADC
SIGNAL (programming language)
Mixed-signal integrated circuit
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Summary The analog‐to‐digital converters (ADCs) play a very important role in electronic products, radar, communication systems and signal processing, to name such a few. In this paper, a novel all‐metal‐oxide semiconductor (MOS) flash‐like analog‐to‐digital converter (FLADC) that consists of five stages is proposed. The design was performed using only MOS transistors, and the proposed ADC works in a way similar to the conventional flash ADC. According to the proposed ADC, there is no need for the comparators used in the conventional flash ADCs, thus resulting in a reduction in both the transistor count and the power consumption. The sound operation and the superiority of the proposed ADC compared to previous works is verified by simulation using the 0.13‐μm complementary MOS (CMOS) technology with a power‐supply voltage, V DD , of 1.2 V. The simulation has been conducted on a 5‐bit FLADC that is built by 276 MOS transistors only which is approximately 32% of the transistor count of the corresponding conventional flash ADC and has no resistors. According to the simulation results, the proposed 5‐bit FLADC consumes 3.23 mW at sampling rate of 0.5 GS/s.
Flash ADC
Analog-to-digital converter
Successive approximation ADC
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A monolithic, 8-bit, 250 megasample per second analog-to-digital converter (ADC) fabricated in an oxide-isolated bipolar process is described. The use of a flash ADC architecture at high speeds without a sample and hold leads to a number of error sources. The design of the converter is optimized to minimize the effects of these error sources. Experimental results are presented and compared with theory.
Analog-to-digital converter
Flash ADC
Bit (key)
Successive approximation ADC
Sample and hold
4-bit
Sample (material)
Digital-to-analog converter
12-bit
Integrating ADC
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The analog to digital converter (ADC), a bridge between digital world and analog world, plays a crucial role in the modern semiconductor industry. Among different types of ADCs, the flash ADC (also known as the direct-conversion ADC) is exceedingly fast, whose high sample rate enables many large bandwidth applications, such as optical communication, radar detection. The comparator circuit is one of the critical components of flash ADC. The characteristics, like latency, gain and power consumption, of comparators determine the overall performance of flash ADCs. This paper analyzes and compares different types of comparator architecture and suggests a high-performance design for flash ADC.
Flash ADC
Analog-to-digital converter
Successive approximation ADC
Sample and hold
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An analog to digital converter is a mixed signal device which converts an analog electrical signal into digital data. Thus they form the front end of any digital circuit in real life signal processing. Looking at the industry progress in recent years, the need to design an compact low power, high speed and wide bandwidth ADC has increased. There have been different architectures of ADCs which are designed with evolution of electronic components. One such type of ADC is Flash ADC which is fastest in its operation at the cost of large circuitry. Applications which require low power consumption with more speed and more resolution preferably choose Folding and Interpolating (F/I) ADC architecture. This work focuses on reducing the analog circuitry of Flash ADC. The design of the circuit is done in Cadence Virtuoso with CMOS 90 nm technology.
Flash ADC
Analog-to-digital converter
Successive approximation ADC
Mixed-signal integrated circuit
Folding (DSP implementation)
Digital-to-analog converter
Analog front-end
Cadence
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Ultra-Wideband (UWB) communication is a recent high speed wireless technology that uses sub-nano second pulses to transmit information. According to United States Federal Communications Commission (FCC), a UWB technology is a form of wireless communication in which signals occupy a wide bandwidth, greater than the lesser of 500MHz or 20% of the center frequency of the signal is consider as an ultra wide band signal. A high speed low/medium resolution Analog-to-Digital converter (ADC) is required for processing the UWB signal. Considering latency and conversion speed, the flash ADC is often the most preferred selection in high-speed communication applications. Therefore, a 5-bit Flash ADC with 500Msamples/s sampling rates has been analyzed and designed. This 5-bit Flash ADC requires 31 comparators, resistor ladder of 32 resistors and thermometer-to-binary code converter (TC-to-BC). This ADC consumes 13.64mw from 1.8V supply voltage at 500MS/s with total conversion time of 1.135ns. The simulations of all the designs are done in cadence UMC 0.18μm technology with a 1.8V power supply.
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Successive approximation ADC
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Analog-to-Digital Converters (ADCs) are useful building blocks in many applications such as a data storage read channel and an optical receiver because they represent the interface between the real world analog signal and the digital signal processors. Many implementations have been reported in the literature in order to obtain high-speed analog-todigital converters (ADCs). In this paper an effort is made to design 4-bit Flash Analog to Digital Converter [ADC] using 180nm cmos technology. For high-speed applications, a flash ADC is often used. Resolution, speed, and power consumption are the three key parameters for an Analog-to-Digital Converter (ADC). The integrated flash ADC is operated at 4-bit precision with analog input voltage of 0 to 1.8V. The ADC has been designed, implemented & analysed in standard gpdk180nm technology library using Cadence tool.
Flash ADC
Analog-to-digital converter
Successive approximation ADC
Delta-sigma modulation
12-bit
Integrating ADC
Digital-to-analog converter
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