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    Analysis and design of Flash analog to digital converter for ultra wide band application
    Nirma University International Conference on Engineering (2011)
    Piyush. V. KanodiyaAmisha Naik
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    Abstract:
    Ultra-Wideband (UWB) communication is a recent high speed wireless technology that uses sub-nano second pulses to transmit information. According to United States Federal Communications Commission (FCC), a UWB technology is a form of wireless communication in which signals occupy a wide bandwidth, greater than the lesser of 500MHz or 20% of the center frequency of the signal is consider as an ultra wide band signal. A high speed low/medium resolution Analog-to-Digital converter (ADC) is required for processing the UWB signal. Considering latency and conversion speed, the flash ADC is often the most preferred selection in high-speed communication applications. Therefore, a 5-bit Flash ADC with 500Msamples/s sampling rates has been analyzed and designed. This 5-bit Flash ADC requires 31 comparators, resistor ladder of 32 resistors and thermometer-to-binary code converter (TC-to-BC). This ADC consumes 13.64mw from 1.8V supply voltage at 500MS/s with total conversion time of 1.135ns. The simulations of all the designs are done in cadence UMC 0.18μm technology with a 1.8V power supply.
    Keywords:
    Flash ADC
    Analog-to-digital converter
    Successive approximation ADC
    Topics:
    Analog and Mixed-Signal Circuit Design
    Advancements in PLL and VCO Technologies
    Low-power high-performance VLSI design
    시간-보간법을 활용한 5-bit FLASH ADC
    융합정보논문지(구 중소기업융합학회논문지) (2021)
    남재원조영균
    본 연구는 시간-보간법을 적용한 FLASH analog-to-digital converter (ADC)에 관한 것이다. 시간-보간 법은 기존의 FLASH ADC에서 요구되는 전압영역 비교기의 개수를 줄일 수 있으며 이 따른 전력 소모 및 칩 면적 의 절약을 기대할 수 있다. 본 연구에서는 5-bit, 즉 31개의 양자화 레벨을 갖는 ADC를 설계 및 구현하였으며, 16개의 양자화 레벨은 기존의 전압영역 비교기 방식을 유지하고, 나머지 15개의 양자화 레벨은 시간영역 비교기 를 통하여 처리되도록 구성하여, 기존 5-bit FLASH ADC 대비 전압영역 비교기의 숫자를 48.4% 줄일 수 있었다. 시제품은 14 nm Fin Field-effect transistor (FinFET) 공정으로 제작되었으며 구현면적은 0.0024 mm2, 전력 소모는 0.8 V 전원전압에서 0.82 mW로 측정되었으며, 400 MS/s의 변환속도 21 MHz 정현파 입력에 대하여 ADC는 28.03 dB의 신호-대-잡음비 (SNDR), 즉 4.36 유효비트(ENOB)의 성능을 보였다.
    Flash ADC
    Successive approximation ADC
    Analog-to-digital converter
    Bit (key)
    4-bit
    Citations (0)
    A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS
    Symposium on VLSI Circuits (2010)
    Ying-Zu LinChun-Cheng LiuGuan‐Ying HuangYa-Ting ShyuSoon-Jyh Chang
    This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. The flash ADC controls thermometer MSBs of the DAC and SAR ADC controls the binary LSBs. The segmented DAC improves DNL during MSB transitions. The merged switching of MSB capacitors enhances operation speed. The 9-bit 150-MS/s ADC consumes 1.53 mW from a 1.2-V supply. The ENOB is 8.69 bit and ERBW is 100 MHz. The FOMs at 1.2 V, 150 MS/s and 1 V, 100 MS/s are 24.7 and 17.7 fJ/conversion-step, respectively. At 1.3-V supply voltage, the sampling rate achieves 200 MS/s.
    Successive approximation ADC
    Flash ADC
    Bit (key)
    12-bit
    Citations (51)
    Behavior-Level Analysis of a Successive Stochastic Approximation Analog-to-Digital Conversion System for Multi-Channel Biomedical Data Acquisition
    IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences (2017)
    Sadahiro TaniToshimasa MatsuokaYusaku HiraiToshifumi KurataKeiji Tatsumi
    In the present paper, we propose a novel high-resolution analog-to-digital converter (ADC) for low-power biomedical analog front-ends, which we call the successive stochastic approximation ADC. The proposed ADC uses a stochastic flash ADC (SF-ADC) to realize a digitally controlled variable-threshold comparator in a successive-approximation-register ADC (SAR-ADC), which can correct errors originating from the internal digital-to-analog converter in the SAR-ADC. For the residual error after SAR-ADC operation, which can be smaller than thermal noise, the SF-ADC uses the statistical characteristics of noise to achieve high resolution. The SF-ADC output for the residual signal is combined with the SAR-ADC output to obtain high-precision output data using the supervised machine learning method.
    Successive approximation ADC
    Flash ADC
    Analog-to-digital converter
    Integrating ADC
    Shaping
    Citations (3)
    A 12-bit 1-MS/s 26-μW SAR ADC for Sensor Applications
    Physical Sciences Reviews (2016)
    Yung‐Hui ChungChia‐Wei YenCheng‐Hsun Tsai
    Abstract This chapter presents an energy-efficient 12-bit 1-MS/s successive approximation register analog-to-digital converter (ADC) for sensor applications. A programmable dynamic comparator is proposed to suppress static current and maintain good linearity. A hybrid charge redistribution digital-to-analog converter is proposed to decrease the total capacitance, which would reduce the power consumption of the input and reference buffers. In the proposed ADC, its total input capacitance is only 700 fF, which greatly reduces the total power consumption of the analog frontend circuits. The 12-bit ADC is fabricated using 0.18-μm complementary metal-oxidesemiconductor technology, and it consumes only 26 μW from a 1 V supply at 1-MS/s. The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 60.1 and 72.6 dB, respectively. The measured effective number of bits (ENOB) for a 100 kHz input frequency is 9.7 bits. At the Nyquist input frequency, the measured SNDR and SFDR are 59.7 and 71 dB, respectively. The ENOB is maintained at 9.6 bits and the figure-of-merit is 33.5 fJ/conversion-step.
    Spurious-free dynamic range
    Successive approximation ADC
    Analog-to-digital converter
    Figure of Merit
    Linearity
    12-bit
    Nyquist rate
    Citations (3)
    A design of 10-bit, 10 MS/s Pipelined ADC with Time-interleaved SAR
    Microelectronics Journal (2017)
    Byeong-Gi JangAbbas Syed HayderSung-Han DoSungHun ChoDongsoo Lee
    This paper presents a 10-bit, 10 MS/s pipelined ADC with a time-interleaved SAR. Owing to the shared multiplying-DAC between the flash ADC and the multi-channel-SAR ADC, the total capacitance of the SAR ADC is decreased by 93.75%. The proposed ADC architecture can therefore provide a higher resolution than the conventional time-interleaved flash-SAR ADC. The proposed 10-bit, 10 MS/s ADC achieves a 9.318-bit ENOB and a figure-of-merit of 357.11 fJ/conversion-step. The ADC that consumes 2.28 mW under a supply voltage of 1.2 V was fabricated in 0.13 µm CMOS and occupies an area of only 0.21 mm2.
    Successive approximation ADC
    Flash ADC
    12-bit
    Bit (key)
    Figure of Merit
    Citations (1)
    A 3-bit 20GS/s interleaved flash analog-to-digital converter in SiGe technology
    Yuan YaoXuefeng YuDayu YangFoster DaiDavid Irwin J.
    A 3-bit analog-to-digital converter (ADC) for software defined radio applications that can work at a sampling rate of 20 GS/s is presented in this paper. In order to operate at Ku-band, two flash current mode logic (CML) ADCs are time-interleaved to achieve a 20 GHz sampling rate. A 3-bit current-steering digital-to-analog converter (DAC) is also designed for testing the high-speed ADC. The ADC-DAC RFIC is implemented in a 0.12 mum SiGe technology and occupies an area of 1.5 times 1.7 mm 2 . The total power consumption for the entire ADC-DAC chip is 2.36 W with a 4.2 V power supply. The ADC-DAC RFIC is packaged in a 44-pin CLLC package and achieves a peak spurious free dynamic range (SFDR) of 30.5 dBc and a peak effective number of bits (ENOB) of 2.8 bits at a 20 GS/s sampling rate.
    Flash ADC
    Spurious-free dynamic range
    RFIC
    Analog-to-digital converter
    dBc
    Citations (10)
    A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS
    IEEE Transactions on Circuits and Systems I Regular Papers (2013)
    Ying-Zu LinChun-Cheng LiuGuan‐Ying HuangYa-Ting ShyuYen‐Ting Liu
    This paper presents a 9-bit subrange analog-to-digital converter (ADC) consisting of a 3.5-bit flash coarse ADC, a 6-bit successive-approximation-register (SAR) fine ADC, and a differential segmented capacitive digital-to-analog converter (DAC). The flash ADC controls the thermometer coarse capacitors of the DAC and the SAR ADC controls the binary fine ones. Both theoretical analysis and behavioral simulations show that the differential non-linearity (DNL) of a SAR ADC with a segmented DAC is better than that of a binary ADC. The merged switching of the coarse capacitors significantly enhances overall operation speed. At 150 MS/s, the ADC consumes 1.53 mW from a 1.2-V supply. The effective number of bits (ENOB) is 8.69 bits and the effective resolution bandwidth (ERBW) is 100 MHz. With a 1.3-V supply voltage, the sampling rate is 200 MS/s with 2.2-mW power consumption. The ENOB is 8.66 bits and the ERBW is 100 MHz. The FOMs at 1.3 V and 200 MS/s, 1.2 V and 150 MS/s and 1 V and 100 MS/s are 27.2, 24.7, and 17.7 fJ/conversion-step, respectively.
    Successive approximation ADC
    Flash ADC
    Linearity
    Shaping
    Analog-to-digital converter
    Citations (76)
    12-Bit SAR ADC Design in SCL 180 nm for Sensor Interface Applications
    Lecture notes in electrical engineering (2023)
    Abhishek KumarAbhishek SahuAnurag DwivediShree Prakash Tiwari
    Successive approximation ADC
    12-bit
    Analog-to-digital converter
    Cadence
    8-bit
    Bit (key)
    SIGNAL (programming language)
    Citations (0)
    A 4-bit 2GSamples/s parallel Flash ADC using comb-type reference ladder
    IEICE Electronics Express (2008)
    Won-Joo YunDongsuk ShinSuki Kim
    This paper describes a 4bit parallel flash Analog-to-Digital converter (ADC) using two sub Flash ADCs and comb-type reference ladder. High speed full flash ADCs have been suffered from input referred noise which is noise itself of analog input or noise inferred from reference ladder. As power supply voltage goes lower and resolution goes higher, noise inferred from reference ladder becomes more critical to ADC's performance. The proposed ADC consists of two parallel sub-ADCs with divided reference ladder to overcome degradation due to small reference voltage step. Simulation results show that the proposed ADC achieves 3.96 effective number of bit (ENOB) for 46MHz input signal and 3.94 ENOB for 1046MHz input signal at 2GHz sampling rate. At 2GSample/s, the current consumption is 45mA including digital logic with 1.8v power supply voltage. The proposed 4bit ADC is designed with 0.18um CMOS technology.
    Flash ADC
    Analog-to-digital converter
    Successive approximation ADC
    Integrating ADC
    Citations (0)
    A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS
    IEEE Transactions on Circuits & Systems II Express Briefs (2008)
    Hai-Rong YuMau-Chung Frank Chang
    We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5–bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.
    Flash ADC
    Spurious-free dynamic range
    Analog-to-digital converter
    Linearity
    Successive approximation ADC
    12-bit
    Nyquist rate
    Delta-sigma modulation
    Nyquist–Shannon sampling theorem
    Citations (62)