Wafer Level Packaging Cost Modeling
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Abstract:
Wafer level packaging is often the most cost effective approach to achieve miniaturization. However, if it is used for the wrong application, it can be very expensive. The significant difference in printed circuit board interconnect design rules and semiconductor interconnect design rules must be addressed in any type of packaging approach, and presents unique challenges for wafer level packaging. If miniaturization is not required, this translation of semiconductor design rules to PCB design rules is most easily accomplished in a traditional wire bond package. However, when the package size and the die size must be the same, the package IO count is limited. Fanout WLP is an option to overcome the WLP IO restriction, but still achieve cost effective miniaturization. We will present the results of activity based cost and yield modeling of traditional wafer level packaging, fanout wafer level packaging, and flip chip packaging across a range of die sizes, package sizes, and defect densities. These results will show the most cost effective technology to match a variety of applications and package parameters.Keywords:
Wafer-level packaging
Chip-scale package
Wire bonding
Wafer testing
Manufacturing cost
Integrated circuit packaging
Wafer-scale integration
Electronic Packaging
Packaging engineering
IBM created the wafer processing technology and concepts more than 45 years ago that would later enable what we call Wafer Level Packaging. With its introduction of the Controlled Collapse Chip Connect (C4) solder bumping process for use in its Solid Logic Technology package, it paved the way for the larger solder bump technology that enabled die to be mounted directly on circuit boards using standard surface mount equipment, and standard pitch circuit board technologies. Over ten years ago, Wafer Level Chip Scale Packaging (WLCSP) came into volume production, with all of the "packaging" done while still in wafer form. It began slowly, with very small packages having solderball counts of 2-6 I/Os. Over the years, the production volumes have grown, and so has the I/O count. Much of the industry still perceives WLCSPs as limited to low I/O count simple applications. However, within the last few years, there have been growing demands for WLCSP packages with I/O counts of 300 and greater, and with higher levels of complexity.
Wafer-level packaging
Wafer-scale integration
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Wafer level packaging is often the most cost effective approach to achieve miniaturization. However, if it is used for the wrong application, it can be very expensive. The significant difference in printed circuit board interconnect design rules and semiconductor interconnect design rules must be addressed in any type of packaging approach, and presents unique challenges for wafer level packaging. If miniaturization is not required, this translation of semiconductor design rules to PCB design rules is most easily accomplished in a traditional wire bond package. However, when the package size and the die size must be the same, the package IO count is limited. Fanout WLP is an option to overcome the WLP IO restriction, but still achieve cost effective miniaturization. We will present the results of activity based cost and yield modeling of traditional wafer level packaging, fanout wafer level packaging, and flip chip packaging across a range of die sizes, package sizes, and defect densities. These results will show the most cost effective technology to match a variety of applications and package parameters.
Wafer-level packaging
Chip-scale package
Wire bonding
Wafer testing
Manufacturing cost
Integrated circuit packaging
Wafer-scale integration
Electronic Packaging
Packaging engineering
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There is a need for miniaturizing electronic components such as ICs and modules that are used in portable devices like cellular phones and PDAs. Miniaturization not only results in a reduced foot print of the components on the printed board but it can also have a positive effect on the device performance. The ultimate miniaturization is reached when packaging the component into a chip size package (CSP). To enable this, the bonding pads of ICs can be rerouted into, e.g., a ball grid array (BGA) configuration. For devices such as vertical discrete components and stacked dies planar rerouting is not sufficient. Introducing so-called through wafer interconnect enables addressing the back side and so these devices can be converted into CSPs. Although through wafer interconnect requires rather complicated technologies, wafer level processing (resulting in simultaneous fabrication of large number of packages) limits the additional packaging cost.
Ball grid array
Chip-scale package
Electronic Packaging
Wafer-level packaging
Wafer-scale integration
Electronic component
Interposer
Wafer testing
Surface-mount technology
Integrated circuit packaging
Wafer Bonding
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A wafer-level packaging (WLP) technology is under development that provides compliant electrical leads with a density as high as 12,000 per cm/sup 2/. The leads are batch processed while the integrated circuits are still in wafer form through a series of relatively simple photolithographic steps. After electrical testing, the wafers are diced and the integrated circuits (ICs) are ready for direct assembly to an interconnect substrate. Sufficient lateral and vertical compliance is provided by the leads to accommodate the nonplanarity encountered during assembly and the thermal mismatch between the IC and substrate during normal operation. The high density of compliant leads presents both challenges and opportunities for electrical testing. This paper first summarizes the process technology used to fabricate these high-density electrical contacts. Several potential test strategies are then introduced that may take advantage of these contacts.
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Wafer-scale integration
Wafer testing
Integrated circuit packaging
Electronic Packaging
Packaging engineering
Electrical contacts
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The author reviews some basic mechanical design approaches available to assure reliable interfaces within and between packaging levels in the chip, package, and circuit-board assemblies. While the approaches can be applied to traditional circuit-board and hybrid assemblies emphasis is placed on the hybrid wafer-scale integration multichip module packaging technologies. It is concluded that a combination of recently available packaging materials of improved properties, recently developed improved analysis techniques, and the advantages of the new hybrid wafer-scale integration technology offers the opportunity to design significantly improved reliability into the next generation of military electronic equipment. Additionally, the equipment size and weight can be reduced significantly. A dramatic demonstration of the miniaturization possible with these technologies was made on a miniaturized version of a GPS (global positioning system) receiver. >
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A wafer-level batch packaging (WLBP) technology is under development that provides compliant electrical leads with a density as high as 12,000 per cm/sup 2/. The leads are processed while the integrated circuits are still in wafer form through a series of relatively simple photolithographic steps. After electrical testing, the wafers are diced and the ICs are ready for direct assembly to an interconnect substrate. Sufficient lateral and vertical compliance is provided by the leads to accommodate the non-planarity encountered during assembly and thermal mismatch between the IC and substrate during normal operation. The high density of leads presents both challenges and opportunities for electrical testing. This paper summarizes the process technology used to fabricate these high-density electrical contacts. Several potential test strategies are introduced that may take advantage of these contacts.
Wafer-level packaging
Wafer-scale integration
Wafer testing
Packaging engineering
Electrical contacts
Electronic Packaging
Integrated circuit packaging
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The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies, mainly due to the increasing pad densities and the use of novel materials. This results in particular challenges for the chip connection technology (wire bonding & flip chip) as well as the package technology. Some of these problems may be resolved through the use of additional metal and dielectric layers, processed on top of the IC passivation, e.g. to redistribute chip pin-out into a regular array. Such wafer-level packaging techniques may result in significant cost savings in device packaging. They do however also provide new opportunities for the circuit design. These additional layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.
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Semiconductors are currently connected to other system components by three main interconnect technologies: wirebond, TAB and solder bump. These processes are significant contributors to the cost of the bumped wafer. In the packaging industry, there is also a drive for towards wafer level packaging solutions in order to minimize the packaging cost and give high production rates. This paper describes the development of a new wafer level process which minimizes the cost of the bumped wafer that requires bond pad redistribution, and at the same time offers the advantages of a wafer level packaging solution. The process is based on the concept of a build up technology that channels the bond pads to a large pitch array in order to make the interconnection to the board. The packaging technology is suited to high frequency, small size, lightweight applications. This process has the potential to drive the industry away from wire bonding to a single step wafer level interconnection process. The paper also provides the results of the characterization that was performed on the package.
Wafer-level packaging
Wafer testing
Wire bonding
Die preparation
Wafer-scale integration
Electronic Packaging
Chip-scale package
Wafer Bonding
Integrated circuit packaging
Wafer backgrinding
Semiconductor device fabrication
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The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment. Dies are packaged and encapsulated into separate enclosures while still in wafer form. This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell. The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection. A proprietary compliant polymer layer under the bumps provides on board reliability. Bumps are placed on the individual contact pads, are reflowed, and wafer singulation yields finished packaged devices. This WLCSP fully complies with Joint Electron Device Engineering Council (JEDEC) and surface mount technology (SMT) standards. Such chip scale packages (CSP's) measure 300-700 /spl mu/m in thickness, a crucial factor for use in various size sensitive electronic products.
Chip-scale package
Wafer-level packaging
Wafer-scale integration
Die preparation
Surface-mount technology
Wafer testing
Electronic Packaging
Integrated circuit packaging
Packaging engineering
Wafer backgrinding
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