Single MetalGatewithDualWorkFunctions forFD-SOIandUTBDoubleGateTechnologies
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In thispaper,we demonstrate an integratable single metalgate(TiSiN) onHfSiXOy with dualworkfunctions (4.44eV and4.83eV), achieved by varying themetalthickness. Thesestructures maybe usedforFD-SOIanddoublegateultra-thin body devices. Close tosymmetric Vtisachieved: 0.32Vand -0.37Vforlongchannel FD-SOInMOS andpMOS devices, respectively. Thedevice showsgoodsub- threshold slopevalues, aslowas62mV/decand 75mV/dec for1tmand0.2pmdevices, respectively. INTRODUCTION:High-k dielectric andmetal gate technologies areofgreat interest inimproving MOSFET performance andreducing gateleakage current. For ultra-thin bodydevices, metalgates withdualwork functions nearthemidgap energy ofsilicon (-4.4eV for NMOS and-4.8eVforPMOS)andanundoped or lightly doped bodyaredesirable (1,2). Thispaper describes thefabrication andresults forFD-SOIdevices using asingle metal withtunable workfunction obtained byvarying themetal thickness; 25ATiSiNwithaworkfunction of4.44eVand225A TiSiNwithaworkfunction of4.83eV. Thisapproach provides agreat advantage inadjusting thethreshold voltage andenhancing theperformance ofn-channel and p-channel devices, whileallowing foranundoped or lightly doped channel. Thethreshold voltages arelower thanifasingle metal gatewithmidgap workfunction (3)wereused. Itprovides another advantage inmeeting therequirement ofscaling downthepowersupply voltage forultra-thin bodydevices. Hafnium silicate is usedasthegatedielectric toreduce thegateleakage. FABRICATION:200mm SOIbondedwafers with initial bodythickness of700Aandburied oxide thickness of1450Awereusedforthedevices. TheSOI layer wasthinned downto200Abythermal oxidation andwetetching. A 40AHfSiOy gatedielectric was deposited byALD,followed byNH3nitridation. A 200A TiSiNfilmwasdeposited byCVD onthewafer. After that, a hardmaskwasformed toprotect thePMOS region, andawetetchremoved alltheTiSiNinthe NMOS area.Thehardmask wasremoved subsequently, and25ATiSiNwasdeposited onthewafer. A 1000A amorphous silicon film wasdeposited tocomplete the electrode. 300Athick selective silicon epilayer was grownontheS/Dregions. Cobalt silicidation andfinal back-end processing wereused. Noprocess induced or substrate induced stress wasusedtoincrease thedevice performance inthis work.A cross-sectional TEM ofthe thin TiSiN metal gate (NMOS)isillustrated inFig. 1. ELECTRICALRESULTS:Effective workfunction extraction ofTiSiN withdifferent thicknesses forpMOS (4.83 eV)andnMOS(4.44 eV)wasdoneoncapacitors using theterraced oxide method(4), asshowninFigs. 2aand2b,respectively. Thesesymmetric workfunctions around thesilicon mid-gap fordifferent TiSiNmetal gatethicknesses offer agreat benefit forultra-thin body device integration duetothesimple andcontrollable processes. Thisworkfunction tuning results innear symmetric Vt'sof0.32Vand-0.37VfornMOS and pMOSrespectively (long channel, linearly extrapolated). TheIds vs.VgsandIds vs.Vdscurves for1ptmand0.2ptm devices areshowninfigs. 3a,3b and4a,4b, respectively. Figs5,6and7showgoodcontrol ofshort channel effects, indicated bysubthreshold slope (62 mV/decand75mV/decforLg=1pImand0.2ptm), DIBL (24mVand5OmVforLg=1(im and0.2ptm), andVT roll-off, respectively. TheIonvs.loff curveisillustrated inFig. 8.Thesilicidation andcontact etch process here hasnotbeenfully optimized forFD SOI,andhence the devices suffer fromhighseries parasitic resistance, as confirmed byShift andRatio measurements (5). The effective electron mobility atthefront interface was extracted using thesplit C-Vtechnique onlong channel devices (6), andisshownversus effective electric field inFig. 9.Peakelectron mobility of 322cm2/V.s was achieved, corresponding toa38%degradation compared totheuniversal mobility; further optimization ofthe high-k process should improve this. Thedegraded mobility andhighparasitic resistance havereduced the Idsat inFigs. 4aand4b. CONCLUSION:A simple single metalgatewith tunable workfunction byvarying TiSiNthickness has beendemonstrated inthis work.Theworkfunctions of 25Aand225ATiSiNaresymmetric around thesilicon mid-gap, resulting innearly symmetric threshold voltages forFD-SOIdevices. Thisoffers a simple integratable solution forUTBdevices.Cite
High-k dielectric oxides have been used to replace the widely used silicon dioxide (SiO2) gate dielectrics to overcome physical limits of transistor scaling. The thickness of high-k gate dielectric influences the threshold voltage (VTH) and off-state leakage current (IOFF). A device with high drive current (ION) and low IOFF gives a high on-off current ratio (ION/IOFF), which leads to a faster switching speed for the Ntype Metal Oxide Semiconductor Field Effect Transistor (NMOS). In order to achieve the best ION/IOFF ratio for a predetermined range of VTH, halo implant was used to adjust the threshold voltage. The finding shows that optimum VTH and ION/IOFF ratio can be achieved by selecting the most suitable halo implant dose in a virtually fabricated 14nm gate-length La2O3-based NMOS device with varying high-k dielectric oxide thickness.
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This work demonstrates a p-MOSFET with a GaNM.l 0.2 Ga 0.8 N (20 nm)/GaN heterostructure grown by metal-organic-chemical vapor deposition (MOCVD) on 6-inch Si substrate with optimized self-aligned process. Devices with source-to-drain distance, L SD , varying from 1 μm down to 200 nm were fabricated. Significant field-induced acceptor ionization was found in these devices at high drain voltages. The device with L SD =200 nm shows a record combination of I ON of ~45 mA/mm and ON-OFF ratio of ~10 4 when compared with other p-channel transistor demonstrations. The device also exhibits Enhancement-mode operation with threshold voltage of -0.5V. The best device shows an ON-current of 100 mA/mm but at the expense of lower on-off ratio of ~10 2 .
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A GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) using tri-gate architecture and hybrid ferroelectric charge trap gate stack is demonstrated for normally-off operation. Compared with the conventional planar device, the tri-gate device has the 2-D electron gas (2-DEG) channel exposed on the nanowire sidewalls, so that the trapped charges in the HfON charge trapping layer can easily deplete the channel from the sidewalls, leading to a high positive threshold voltage (V th ) to realize the normally-off operation. Moreover, through this electrostatic control on the sidewall, a high density of negative charge caused by hybrid ferroelectric charge trap gate stack with the optimized tri-gate structure, the tri-gate device can achieve normally-off GaN device with both low on-resistance (R ON ) and high positive V th . The designed tri-gate device exhibits a high V th of +2.61 V at current density (I DS ) = 1 μA/mm, a high maximum current density (IDS, MAX) of 896 mA/mm, a low R ON of 5.0 Ω·mm and a high breakdown voltage (BV) of 788 V. To the best of our knowledge, the proposed tri-gate device shows the lowest specific on-resistance (R ON ,SP) among reported normally off GaN device results with BV > 650 V.
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nm self-aligned n- and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 μA and 355.4/8.9 μA per μm, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.
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Nowadays most of the industrial technology in fabrication of transistors is based on the use of semiconductor junctions. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms in the semiconductor, the formation of ultra-shallow junctions with high doping concentration gradients has become an increasingly difficult challenge for the semiconductor industry. Thus, scaling-down of semiconductor devices, which remarkably follows Moore's law during the last 40 years, has pushed complementary metal–oxide–semiconductor (CMOS) devices close to fundamental limits. In order to keep the validity of Moore's law, device down scaling is not enough. So called material and geometry technology boosters have been introduced. High-k dielectrics, silicon-on-insulator substrates or strained silicon are some booster examples that were used at sub-micron scale.
In this work, unconventional technique of atomic force microscopy (AFM) nanolithography via local anodic oxidation process was performed to fabricate junctionless lateral gate silicon nanowire transistors (JLGSNWTs) which have no
physical junction and no dielectric material. We have chosen to use the oxidation by AFM in contact mode. This process was applied to a lightly doped (1015 cm−3) p-type
(100) silicon on insulator (SOI) wafer with top silicon thickness of 100 nm and a 200 nm buried oxide (BOX) thickness with a resistivity of 13.5–22.5 Ω cm. Modified RCA
cleaning process and hydrofluoric acid (HF) etching used in order to prepare the sample for further fabrication steps. By examining different voltage bias ranging from 3-10 V,
writing speed ranging from 0.1-10 μm/s, and different environmental condition (temperature and humidity), we optimized the fabrication parameters. Applying a 9 V
voltage to a Cr/Pt tip, while it was scanning once over the silicon surface at speed of 1 μm/s, led to a 2–3 nm-thick oxide pattern of width 80–90 nm which was the smallest
reproducible dimensions achieved. Humidity was maintained in the range of 55%-68%. An anisotropic wet chemical etching process was performed to remove uncovered
portion of the structure. Solutions of 30 and 40 wt% Potassium Hydroxide (KOH), saturated with isopropyl alcohol (IPA) at the temperature range of 60 - 80 were used to remove all the non protected silicon areas. The best results achieved are at 30 wt% and 65 . The electrical characteristics of the JLGSNWTs were measured by an
HP4156C semiconductor parameter analyzer (SPA, Agilent) at room temperature. The device showed the characteristic similar to normal MOSFET; however the principle of operation is completely different. The output characteristics of the fabricated device with 100 nm nanowire width, 100 nm nanowire thickness, 4.2 μm nanowire length, and 100 nm gate gap shows an ION/IOFF ratio in the order of 105.
Since the device structure was new and operational principle of transistor was not clear, thus, the same structure was simulated using Technology Computer-Aided Design (TCAD). In order to do, Sentaurus software tool is used as the platform for the 3D TCAD simulation. The output characteristic has been compared with the experimental
results and critical physical quantities such as carries density, electric field configuration, carriers‘ recombination-generation possibility, and carriers‘ mobility
which affects the characteristics of the device has been carefully investigated. The analysis of the extracted parameters from the simulation revealed that the JLGSNWTs
are normally on devices which by applying positive voltage to the lateral gates turn the devices off based on the pinch off mechanism, but increasing negative gate voltages
were not able to improve the current significantly. The saturation current is proportional to the device cross width, thickness, the channel length, the semiconductor nanowire doping density, and a voltage which obeying Vch ≤ Vds, and not to the gate capacitance.
In addition, devices which from technical point of view were difficult or too expensive to be fabricated have been investigated by simulation process. Effect of nanowire length (S/D distance), channel length (area under the gate), nanowire width, nanowire thickness, and gate gap on behavior of device has been investigated. It has been observed that decreasing the nanowire length increases the output current due to the change in electric field configuration in the gates position from 2.0 10 3 V.cm-1 for a device with 4.2 μm nanowire length to 6.0 x 103 V.cm-1 for a device with 1 μm nanowire length. Channel length was more effective when the positive gate voltage applied to the lateral gates. The ION/IOFF varies from 102 for device with 50 nm channel length to 109 for device with 400 nm channel length. Because of the symmetry of the structures the effect of channel width and channel thickness was quite the same. The narrower and thinner structures presented lower off current and better control of gates on the behavior of carriers. The gate gap is another parameter which affected the behavior of the device due to the change of electric field magnitude which directly
affect carriers‘ density and mobility of the carriers.
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In this work, threshold voltage modulation realized by adjusting fin width and dielectric layer were investigated through MIS-FinFETs. As fin width decreases from 120 to 30 nm, threshold voltage shifts toward positive direction and finally becomes positive value while maintaining SS smaller than 60 mV/dec. The phenomenon of achieving sub-60 mV/dec characteristics were illustrated by simulation and the concept of effective channel length. As for dielectric layer, by 20 nm-thick SiO 2 dielectric layer, device with fin width of 90 nm exhibits a threshold voltage of -0.5 V with SS as small as 50 mV/dec. Even when fin width is 30 nm, drain leakage is still not small enough when VG = 0, which indicates that the gate is not able to totally deplete the fin structure. In order to further increase threshold voltage and enhance the gate controllability, by 10 nm-thick Al 2 O 3 dielectric layer, a threshold voltage of 2 V is achieved when fin width is 40 nm with SS as small as 52 mV/dec due to the higher dielectric constant and thinner thickness of Al 2 O 3 compared with SiO 2 . Therefore, by the modulation of fin width, dielectric layer type, and dielectric thickness, threshold voltage can be carefully designed according to the application requirements while maintaining SS below 60 mV/dec.
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Transconductance
Insulated-gate bipolar transistor
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Antimonide (Sb) quantum well (QW) MOSFETs are demonstrated with integrated high-κ dielectric (1nmAl 2 O 3 -10nm HfO 2 ). The long channel Sb NMOS exhibits effective electron mobility of 6,000 cm 2 /Vs at high field (2 × 10 12 /cm 2 of charge density (N s )), which is the highest reported value for any III-V MOSFET. The short channel Sb NMOSFET (L G = 150nm) exhibits a cut-off frequency (f T ) of 120GHz, f T - L G product of 18GHz.μm and source side injection velocity (v eff ) of 2.7×10 7 cm/s, at drain bias (V DS ) of 0.75V and gate overdrive of 0.6V. The measured f T and f T × L G are 2 x higher, and v eff is 4× higher than Si NMOS (1.0-1.2V V DD ) at similar L G , and are the highest for any III-V MOSFET.
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We have demonstrated and experimentally verified the advantages of In-Zn-O (InZnO) channel compared with In-Ga-Zn-O (InGaZnO) channel for high performance oxide semiconductor channel field effect transistor (FET) with both ultralow off-state leakage current and high on-current. Compared with InGaZnO FET, high mobility (>30 cm 2 /Vs) and reduction of source/drain (S/D) parasitic resistance by 75% were achieved by InZnO FET. Analysis of a Schottky barrier height at S/D contact and a band offset between oxide semiconductor channel and gate insulator SiO2 revealed that the reduction of S/D parasitic resistance originated from a lowering of conduction band minimum by InZnO channel. Moreover, ultralow (<;10 -20 A/μm) off-state leakage current characteristics including not only S/D leakage current but also gate leakage current were confirmed to maintain even at thin gate insulator with an equivalent oxide thickness of 6.2 nm.
Leakage (economics)
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This paper describes a low leakage n-channel Si gate FET. An n-doped polycrystalline Si field shield was used to achieve low junction leakage. Field shield and diffusion self-alignment was obtained by using a nitride-oxide insulator between the shield and the substrate. A gated diode structure and charge retention cell were used to characterize junction leakage. A -0.5 to -1.0 volt shield-to-substrate bias produced minimum junction leakage. Average minimum leakage, measured at 25°C and 9 volts reverse bias, was 6.5\times10^{-15} A/mil 2 ; corresponding retention time of a charge retention cell was 158 sec. 300Å SiO 2 plus 300Å Si 3 N 4 was used for the gate dielectric. The silicon gate was dopea during the POCl 3 source-drain diffusion process. Average threshold voltage was 0.88 volts (at V SX = -3V); average normalized transconductance, 36.1 micromhos/volt, corresponds to an effective mobility of 525 cm 2 /V-sec. Devices made with a nitride-oxide gate insulator can exhibit a large threshold voltage shift when stressed at elevated temperatures. This shift is caused by the differential conductivity mechanism. The V t shift is greatly reduced by annealing the Si 3 N 4 for 1 hr. in steam at 1000°C prior to silicon gate deposition. This anneal reduces the V t shift from greater than 1V to less than 100mV for devices stressed at 14V, 165°C, and 500 hr.
Leakage (economics)
p–n junction
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