High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme
5
Citation
12
Reference
10
Related Paper
Citation Trend
Abstract:
Among existing works of high-speed pipelined adaptive decision feedback equalizer (ADFE), the pipelined ADFE using relaxed look-ahead technique results in a substantial hardware saving than the parallel processing or Look-ahead approaches. However, it suffers from both the signal-to-noise ratio (SNR) degradation and slow convergence rate. In this paper, we employ the predictive parallel branch slicer (PPBS) to eliminate the dependencies of the present and past decisions so as to reduce the iteration bound of decision feedback loop of the ADFE. By adding negligible hardware complexity overheads, the proposed architecture can help to improve the output mean-square error (MSE) of the ADFE compared with the Relaxed Look-ahead ADFE architecture. Moreover, we show the superior performance of the proposed pipelined ADFE by using theoretical derivations and computer simulation results. A VLSI design example using Avant! 0.35-/spl mu/m CMOS standard cell library is also illustrated. From the post-layout simulation results, we can see that the PPBS scheme requires only 38.4% gate count overhead, but it can help to reduce the critical path from 7.06 to 4.69 ns so as to meet very high-speed data transmission systems.Keywords:
Critical path method
Standard cell
Performance Improvement
All-Spin Logic (ASL) devices provide a promising spintronics-based alternative for Boolean logic implementations in the post-Complementary Metal-Oxide Semiconductor (CMOS) era. In principle, any logic functionality can be implemented in ASL. In practice, the performance of an ASL gate is significantly affected by layout choices, but such implications have not been adequately explored in the past. This article proposes a systematic approach for building standard cells in ASL, which are a basic building block in an overall design methodology for implementing large ASL-based circuits. We first propose a new technique to reduce the magnet count for an ASL majority gate but still ensure correct functioning through layout optimization methods. Building on physics-based analysis, we then build a standard cell library with diverse functionality and characterize the library for delay, energy, and area. We perform delay-optimized technology mapping on ISCAS85 benchmark circuits using our library. Our approach results in circuits that are 12.90% faster, consume 26.16% less energy, and are 33.56% more area efficient compared to a standard cell library that does not incorporate layout-based optimization techniques of our work.
Standard cell
Benchmark (surveying)
Cite
Citations (7)
Delay insensitive circuits can solve several problems of VLSI designs. A synthesis system that automatically generates delay insensitive circuits from behavioral specifications has been developed by means of connection of dedicated standard cells. The electrical characterization of the standard cell set is presented, with emphasis on the new aspects introduced by this field of VLSI design. Complexity and speed parameters of each cell are reported. A first example of layout obtained by the system is present and evaluated.< >
Standard cell
Emphasis (telecommunications)
Cite
Citations (5)
Use of standard cells in the very-large-scale integration (VLSI) design enables very short time to market even for complex microprocessors. Thus, most VLSI layouts are designed using standard cells. In this article, we propose a new design methodology, namely, NP-Separate, to reduce the power consumption and area and increase the performance of a VLSI layout more effectively than the standard-cell-based design methodology. NP-Separate uses N cells and P cells composed of NFETs and PFETs only, respectively, thereby providing a higher degree of flexibility than using standard cells. Our simulation results for several benchmark circuits show that NP-Separate reduces the layout area by 9%, power consumption by 10%, power-delay product by 18%, and energy-delay product by 26% on average while satisfying given timing constraints compared to standard-cell-based designs.
Benchmark (surveying)
Standard cell
Cite
Citations (8)
The project evaluation and review technique (PERT) and critical path method (CPM) were applied in a building construction company. Different activities involved in the house construction project were described. The earliest events, latest commencement and completion of activities were determined using Forward and Backward pass computations in CPM. Critical paths were determined using both CPM and PERT. Based on the analysis, it was shown that the completion of the house project using CPM was almost the same with that of PERT such that the difference between both techniques was only one day.
Critical path method
Cite
Citations (17)
The rules and overall methodology governing standard cell very large scale integration (VLSI) design are described. Standard-cell VLSI design represents a growing trend in custom parts and falls in between the implementation of arrays of logic gates and the implementation of full custom designs. The main advantage of standard cells over gate arrays is the savings in area. In contrast to gate arrays, a standard-cell design does not have predefined sites on the silicon wafer for the cells; thus, the area can be minimized by optimizing the layout and routing for the given design. The penalty is the increased turnaround time from design to actual samples. Gate-array wafers are pre-made, and only a few mask levels need to be added to implement the circuit.
Standard cell
Wafer-scale integration
Turnaround time
Integrated circuit design
Cite
Citations (2)
Very-Large-Scale Integration (VLSI) is the process of establishing integrated circuits. Although the process is getting more and more complex, the development of VLSI has effectively increased the design capability and system performance. Power dissipation for large and complex circuits has always been a concern for engineers on the leading edge of technology. This paper aims at establishing a new standard cell library. Moreover, the most relevant definitions, classifications and details (including power and performance optimization) of the new standard cell library are presented in this paper.
Standard cell
Integrated circuit design
Cite
Citations (0)
Optimization of Cost Function with Cell Library Placement of VLSI Circuits Using Simulated Annealing
VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive solution of the cell placement technique, with emphasis on standard cell and macro cell placement using simulated annealing. The metropolis algorithm is applied to generate generations by decreasing the temperature (cooling coefficient). The state will be accepted or rejected based on energy level (cost) and finally optimum solution will be selected.
Standard cell
Cite
Citations (1)
The design aspects and methodology from concept to manufacture of standard cell VLSI circuits are covered. A broad treatment of the subject and of what design aids are available to help designers get their jobs done efficiently and reliably is provided. The treatment is directed toward the new VLSI designer.
Standard cell
Electronic design automation
Integrated circuit design
Design methods
Cite
Citations (23)
Standard cell
Design methods
Cite
Citations (0)
As part of the Physical Design process for digital circuits, the design is mapped to the cells from a given standard cell library. These libraries contain many different variants of each logical function that may vary in transistor widths, lengths, and threshold voltages. Choosing the right cell for each gate in the design is the discrete gate sizing and threshold assignment problem. Discrete gate sizing and threshold assignment are some of the most powerful and commonly used methods for optimizing power/performance/area in digital circuits. Discreteness of the problem makes it computationally difficult and has attracted significant research attention over the past three decades. Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment surveys this field, providing the background needed to understand the problem and perform research in the area. Concepts such as standard cell libraries, static timing analysis, and analytical delay and power models are explained, along with examples and data to help understand the tradeoffs involved. Popular classes of sizing algorithms are explained and comparative results are provided to show the current state of the field. This is an ideal reference text for graduate students and researchers in electronic design automation, and physical designers looking to improve the performance of their designs.
Standard cell
Cite
Citations (5)