An introduction to standard-cell VLSI design: Very large scale integration (VLSI) is becoming an important means of producing electronic circuits at low cost, on tight schedules, and with protection for proprietary designs
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The rules and overall methodology governing standard cell very large scale integration (VLSI) design are described. Standard-cell VLSI design represents a growing trend in custom parts and falls in between the implementation of arrays of logic gates and the implementation of full custom designs. The main advantage of standard cells over gate arrays is the savings in area. In contrast to gate arrays, a standard-cell design does not have predefined sites on the silicon wafer for the cells; thus, the area can be minimized by optimizing the layout and routing for the given design. The penalty is the increased turnaround time from design to actual samples. Gate-array wafers are pre-made, and only a few mask levels need to be added to implement the circuit.Keywords:
Standard cell
Wafer-scale integration
Turnaround time
Integrated circuit design
Circuit complexity
Register-transfer level
Standard cell
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The NP-Separate design methodology for very-large-scale integration (VLSI) design fine-controls the sizes of transistors, thereby achieving significant power, performance, and area improvement compared to the conventional standard-cell-based design methodology. NP-Separate uses NP cells formed by merging and routing N and P cells having only NFETs and PFETs, respectively. The NP cell formation, however, should be automated to design large circuits using the NP-Separate design methodology. In this paper, we propose design automation algorithms to create NP cells automatically. Simulation results show that the automated NP-Separate reduces the design time significantly, decreases the coupling capacitance by 13%, the critical path delay by 6%, and the power consumption by 10% on average compared to the manual NP-Separate designs. We also propose a detailed placement algorithm to generate more compact VLSI layouts with a little wirelength overhead. The combined effect reduces the coupling capacitance by 10%, the critical path delay by 5%, and the power consumption by 10% on average compared to the manual NP-Separate designs.
Electronic design automation
Standard cell
Critical path method
Design flow
Integrated circuit design
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With the scaling of VLSI technologies, the design-technology co-optimization (DTCO) requires prompt development of standard cell libraries to explore scaling effects of various cell architectures. However, standard cell layout design demands holistic efforts for processing transistor placement and in-cell routing due to the limited routing tracks and complicated design rules. Thus, an automatic design framework of standard cell layout became essential in the advanced scaling. Conventional heuristic/divide-and-conquer approaches lack the optimality of solutions because of the limited solution space. In this paper, we propose a novel standard cell scaling framework that simultaneously finds an optimal solution in placement and routing with the pin-accessibility. To ensure the minimum number of pin-access points, we devise strict Boolean counter-based design constraints. We validate our framework using scaling parameters and cell architectures across sub-7nm technology nodes.
Standard cell
Electronic design automation
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The rules and overall methodology governing standard cell very large scale integration (VLSI) design are described. Standard-cell VLSI design represents a growing trend in custom parts and falls in between the implementation of arrays of logic gates and the implementation of full custom designs. The main advantage of standard cells over gate arrays is the savings in area. In contrast to gate arrays, a standard-cell design does not have predefined sites on the silicon wafer for the cells; thus, the area can be minimized by optimizing the layout and routing for the given design. The penalty is the increased turnaround time from design to actual samples. Gate-array wafers are pre-made, and only a few mask levels need to be added to implement the circuit.
Standard cell
Wafer-scale integration
Turnaround time
Integrated circuit design
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Physical design for digital ICs, based on standard cells, has long been performed without explicit consideration of timing and power related to interconnects. With delays on wires more and more dominating the delays on logic paths, such design styles are becoming obsolete. What is needed is an iterative inclusion of power and timing aspects into the design flow for placement and routing, which yields economic results without multiple loops in the design flow. Basic problems and solutions in the implementation of such a design flow are presented.
Design flow
Standard cell
Integrated circuit design
Static timing analysis
Design methods
Electronic design automation
Register-transfer level
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Summary form only given, as follows. The density of silicon integrated circuits has been increasing by a factor of two per year and this increase can be expected to continue in the forseeable future. This increasing scale of integration requires the use of comprehensive aids in order to prevent the design intervals from becoming excessively long and to limit the expenditure of design resources per circuit. With the increasing density and the trend to larger chips, silicon utilization will not be as critical a consideration as it has been in the past. It is therefore likely that faster turnaround and lower design cost can be achieved at the expense of some silicon area. Turnaround time and design cost considerations will likely cause the design style to become more modular and the use of predesigned blocks will become more common.
Turnaround time
Electronic design automation
Integrated circuit design
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Standard cell
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An expert system for VLSI layout design is introduced. It synthesizes a VLSI layout of a digital logic circuit from a high-level description of the circuit modules and the associated interconnection list. The synthesis process utilizes a standard cell library built within the system and selects a certain module according to a multilevel criterion directed by user-specified importance factors. The system then performs the module placement task, by placing the modules which are tightly interconnected near each other. It then performs the routing task. This routing system is based upon a modified version of a grid expansion router. It contains adjustable parameters to fit the desired technology. It is a computer-aided design tool written in Prolog on a microcomputer, and it is used with different samples of digital circuits.< >
Standard cell
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The layout of integrated circuits involves placing devices in a chip and interconnecting the devices. These terms are named placement and routing. However, conventional algorithms on placement and routing emphasize the initial construction of layout. Little concern is put on changes in placement and routing when there is adjustment of the circuit. In this paper, a new algorithm on layout of digital IC is proposed. The method will save IC designers from re-designing IC layout due to changes in design requirement.< >
Integrated circuit layout
IC layout editor
Page layout
Design layout record
Network routing
Integrated circuit design
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Currently, the design flow of digital integrated circuits relies on the use of pre-characterized libraries. These libraries, pre-calculated outside of any context, are used at each step of the design flow to predict the performance of the circuit. They are necessary for the calculation of a wide variety of characteristics, including the IR Drop. However, the behavior of the logic gates described in these libraries is not representative of the real power supply of the standard-cells and this difference is even more important as the number of logic gates in the circuits increases. In this paper, we will show that with the current design flow, the use of these libraries leads to an underestimation of the circuit performances. To remedy this, we propose an iterative approach based on a new use of voltage-adaptive libraries that allows to compute the IR Drop more precisely and thus to better predict the performances of the circuits.
Design flow
Power network design
Integrated circuit design
Standard cell
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In the recent years, the circuit complexity has been on massive rise. Manual designing of the complex chips are no longer possible. This situation has led to the proliferation of automated Electronic Design Automation (EDA) tools. These have also have lead to the development of the standard cell design methodologies and the semi custom design solutions. The standard cell can be used for a particular function and this eases the design segment manpower and effort. Secondly, the complex circuits in dire necessity of low power operation, necessitates the non-conventional low power design methodologies such as the reversible logic. They play a significant role in the design of digital circuits due to its distinguishing feature of incurring low power dissipation. This paper portrays the design and standard cell characterization of the reversible logic. The Cadence® Liberate tool has been used in the designs and 45nm CMOS technology library files have been employed.
Standard cell
Electronic design automation
Cadence
Integrated circuit design
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