Variability Analysis of TiN Metal-Gate FinFETs
Kazuhiko EndoS. O’uchiYuki IshikawaYongxun LiuTakashi MatsukawaKunihiro SakamotoJunichi TsukadaHiromi YamauchiMeishoku Masahara
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Abstract:
Variability of TiN FinFET performance is comprehensively studied. It is found that the variation of the in the FinFET occurs and the standard deviations of the of nMOS and pMOS FinFETs are almost the same. From the analytical results, it is found that the variation of the TiN FinFET is due to the work function variation (WFV) of TiN metal gate. The WFV is also responsible for the on-current variation.Keywords:
Metal gate
We design a technique to separately measure the Vth of NMOS and PMOS. This technique is used to determine the body bias of NMOS and PMOS individually. Prototype chips with 1Mb 0.51 mm2 high-density SRAM cells using a 65 nm low-power process are fabricated and achieve 1.0 V operation, even when considering actual Vth variation.
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Sustaining Moore's Law of scaling Si CMOS transistors requires not only shrinking the transistor dimensions, but also the introduction of new materials and structures. In the future, advanced high performance CMOS transistors are likely to incorporate highly strained Si and SiGe channels for enhanced carrier transport and high-k/metal-gate stacks for low gate leakage. This work describes the recent advances made in integrating strained Si and SiGe channel transistors with high-k/metal-gate stacks for future high performance, low power logic applications.
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Variability of TiN FinFET performance is comprehensively studied. It is found that the variation of the in the FinFET occurs and the standard deviations of the of nMOS and pMOS FinFETs are almost the same. From the analytical results, it is found that the variation of the TiN FinFET is due to the work function variation (WFV) of TiN metal gate. The WFV is also responsible for the on-current variation.
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The single event transient (SET) susceptibility in the sub-20nm bulk FinFET process is studied in this letter. It is firstly found that NMOS is more sensitive to SET compared with PMOS, which is opposite to the planar CMOS process. A FinFET Technology Computer-Aid Design (TCAD) model is established to research the underlying physical mechanisms. Results show that two factors lead to the difference in SET susceptibility between NMOS and PMOS. First, the drift & diffusion (DD) plays more role than bipolar amplification (BA) in FinFET-PMOS, causing lower SET sensitivity than planar-PMOS. Second, source and drain (S/D) collect more charge in NMOS, causing more sensitivity of SET compared to PMOS.
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The effective work function of PMOS metal gate electrode as a function of intentionally altered HfO 2 surfaces was investigated. The impact of capping layers, diffusion barriers and interfacial layers on the final work function was also examined. The factors responsible for the change in the effective work function after subsequent thermal treatments were identified and routes to maintain the high effective work function have been demonstrated
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