Fabrication and electrical characterization of 5×50um through silicon vias for 3D integration
Bharat BhushanMinrui YuJohn DukovicLoke Yuen WongAksel KitowskiMun Kvu ParkJohn HuaShwetha BolagondAnthony ChanChin Hock TohArvind SundarrajanNiranjan KumarSesh Ramaswami
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Abstract:
We present fabrication, electrical characterization, and metrology analysis results of 5×50um TSVs for 3D integration. Specifically, electrical performance of blind TSVs is evaluated by capacitance-voltage (CV) and current-voltage (IV) measurements. Important electrical parameters such as oxide capacitance, minimum TSV capacitance, leakage current, and breakdown voltage are extracted and show good results. The capacitance values also closely match model predictions. The electrical testing data are further verified with a variety of materials analysis techniques.Keywords:
Characterization
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The capacitance sensor is of simple structure, the resolution ratio is high, temperature stability is good, having a good adaptability, the trends are of good performance, but the existence of the parasitic capacitance has influenced its performance characteristics seriously, the article has analysed the main reason existing in parasitic capacitance of the capacitance sensor , and dispel several kinds of methods that the parasitic capacitance interfere: Is it urge cable technology , operation amplifier urge technology , whole shielding technology , integrated combination technique is it reduce capacitance of depending on for a living to come to adopt mainly, in order to improve the performance of the sensor.
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Differential capacitance
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The parasitic capacitance of a magnetic component, such as an inductor and a transformer, is critical because it can determine component's high frequency impedance, leading to voltage / current spikes, and causing EMI issue. The simulation-based techniques, the measurement-based techniques and the calculation-based techniques are popularly employed to model the parasitic capacitance. Measurement-based techniques are accurate in calculating the parasitic capacitance. The measurement-based techniques are black-box techniques and cannot provide guidelines in reducing the parasitic capacitance during manufacturing. The calculation-based techniques extract the parasitic capacitance based on calculated electric energy. Choosing the winding structure with reduced electric energy can also reduce the parasitic capacitance. However, when calculating the electric energy, the existing techniques are based on the quasi static approximation in which the electric field excited by the time-varying magnetic field is ignored. Simulation issues such as convergence issue exist in the simulation-based techniques. This paper focuses on the solution of comprehensive calculation of all the parasitic capacitance, including both the electrostatic capacitance and the time-varying EM capacitance. It proves that for the magnetic components with ferrite cores, the time-varying EM capacitance can be the dominant capacitance for high frequency magnetic components and it cannot be ignored. Therefore, it explained why the calculated capacitance is not accurate for certain type magnetic components. Furthermore, the paper proposes certain structures to achieve small parasitic capacitance.
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Closed-form expressions of the parasitic insulator capacitance and the substrate capacitance for tapered through silicon vias (TSVs) are proposed. The expressions are functions of the geometric and material parameters of TSVs. They also can be applied to the cylindrical TSVs when the slope angle is zero. The two parasitic capacitances increase as the slope angle increases, which implies that the tapered TSVs have larger capacitances compared with the cylindrical TSVs. Computer Simulation Technology Electromagnetic Studio TM (CST EMS) is used to verify the expressions. The results indicate the maximum errors between the expressions and simulation results for the insulator capacitance and the substrate capacitance are 6.27% and 4.15%, respectively.
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The transient response of a crossbar array is investigated with HSPICE circuit simulation. A crossbar array contains many parasitic elements. This brief focuses on the parasitic capacitances of the selector devices and resistors. The read access time is determined for various array sizes and parasitic capacitances. The results show that the read access time increases with the array size and parasitic capacitance, particularly the selector capacitance. The effect of selector capacitance is analyzed with a time-dependent, unit-cell voltage model and simulation. The simulation results reveal that the selector capacitance has a greater effect than the resistor capacitance on the read access time because of the large time constant. The effect of the selector capacitance on the read access time remains significant for larger values of the other parasitic capacitances.
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A single-ended charge-sharing based capacitance to voltage converter (CVC) which is suitable for the sense of capacitance to ground is described. It uses on-chip capacitor array to provide stable compensation for the input fixed and parasitic capacitance. Three modes are performed successively to detect the absolute values of input fixed and parasitic capacitance, feedback capacitance, compensation error, and input variable capacitance precisely. Simulation results show that the maximum test error of the proposed CVC under different V&T environments is about 0.8 fF, which achieves a high-test resolution for capacitance sensing of a single-ended capacitor.
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We present a general modeling methodology for metal fill parasitic capacitance in on-chip transmission lines. Our approach is based on reducing the problem complexity in all three dimensions. Typical speed-up is 16 fold. The maximum error in self and mutual capacitance is < 6 % and < 10 %, respectively over a wide range of parameters. The agreement with measurements is within 2.1 %. We predict the slow-wave factor of transmission line designs with < 1.2 % error and Q degradation with < 4 % error.
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Common mode current suppression is important to grid-connected photovoltaic (PV) systems and depends strongly on the value of the parasitic capacitance between the PV panel and the ground. Some parasitic capacitance models have been proposed to evaluate the magnitude of the effective parasitic capacitance. However, the proposed model is only for the PV panels under dry and clean environmental conditions. The dependence of rain water on the capacitance is simply described rather than analyzing in detail. Furthermore, the effects of water are addressed quite differently in papers. Thus, this paper gives complete parasitic capacitance model of the PV panel considering the rain water. The effect of the water on the capacitance is systematically investigated through 3D finite element (FE) electromagnetic (EM) simulations and experiments. Accordingly, it is clarified how the water affects the parasitic capacitance and methods of minimization of the capacitance are proposed.
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