Cost analysis of compliant wafer level package
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Abstract:
Low cost package solutions are required by the semiconductor industry to meet the growing demand of high performance and high functionality in electronic products. In particular, the International Technology Roadmap for Semiconductors (ITRS) projects the package cost per pin to be as low as (0.30-1.26 cents) in 1999 to (0.27-0.93 cents) in 2005 to (0.24-0.68 cents) in 2011. To satisfy this need, a Compliant Wafer Level Package (CWLP) technology has been developed that: (a) packages all of the ICs intact on the wafer at once, and (b) fabricates all of the compliant Input/Output (I/O) connections monolithically in one step. Using discrete event simulations, a detailed manufacturing cost model for the CWLP is described. In contrast to the conventional packages where the cost of the package increases with the I/O count, the CWLP cost is independent of the I/O count because all of the I/Os are monolithically fabricated in one step. For 6-inch wafers and throughput greater than 50,000 wafers per year, the manufacturing cost of the CWLP is computed to be $26.65 per wafer. The percent contributions of the material, equipment and labor to the total cost is calculated to be 87%, 9%, and 4%, respectively.Keywords:
Semiconductor device fabrication
Manufacturing cost
Wafer testing
Integrated circuit packaging
Semiconductor device modeling
Wafer-level packaging
This paper presents wafer-level packaging (WLP) solution for RF-MEMS applications based on through-wafer via (TWV) technology in high-resistivity silicon (HRS). A pre-processed HRS capping wafer containing recesses and vertical Cu-plated TWV interconnect is, after alignment, bonded to the RF-MEMS wafer providing environmental protection and easy signal access. Optionally, cavities can be formed simultaneously with TWV in the capping wafer, which allows hybrid co-integration of additional IC dies while maintaining overall thickness of the resulting SMT compatible package. This cavity can also be used for a first-level wafer-to-wafer alignment accuracy check. After bonding, the s-parameter measurement at giga hertz level shows little influence introduced by the capping substrate.
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Wafer level packaging is often the most cost effective approach to achieve miniaturization. However, if it is used for the wrong application, it can be very expensive. The significant difference in printed circuit board interconnect design rules and semiconductor interconnect design rules must be addressed in any type of packaging approach, and presents unique challenges for wafer level packaging. If miniaturization is not required, this translation of semiconductor design rules to PCB design rules is most easily accomplished in a traditional wire bond package. However, when the package size and the die size must be the same, the package IO count is limited. Fanout WLP is an option to overcome the WLP IO restriction, but still achieve cost effective miniaturization. We will present the results of activity based cost and yield modeling of traditional wafer level packaging, fanout wafer level packaging, and flip chip packaging across a range of die sizes, package sizes, and defect densities. These results will show the most cost effective technology to match a variety of applications and package parameters.
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Wire bonding
Wafer testing
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Integrated circuit packaging
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In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.
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The important factors for packaging technology are IC packaging costs, the impact of the package on circuit and system performance, and the reliability of the package. Wafer level packaging technology is a promising solution for future IC generations. This paper reviews the wafer level bumping process and its requirement for thick resist coating and full field aligned exposure. 3D interconnect technology is a viable solution for increasing electronic device functional density and reducing total packaging costs. The critical issue is the ability to align and bond with precision, one micron or less, two silicon wafers or a silicon wafer to another substrate. For CMOS devices, this technology can be applied to chip-scale packaging and also to advanced 3D interconnect processes. In this paper, we describe a new approach to wafer-to-wafer alignment using alignment targets at the bond interface, i.e. face to face wafer alignment (SmartVieW/sup TM/) that relies on precision alignment positioning systems to register and align wafers with one micron or better precision.
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Comparing alternative packaging technologies is a complex task, involving prioritization of cost, performance, and business strategy issues. This paper focuses on one portion of the decision-making equation - cost. Using a tool for assessing the manufacturing costs of electronic packaging, cost outlook scenarios for three advanced packaging technologies are analyzed and compared. The technologies are flip-chip-on-board (FCOB), wafer-scale chip-scale packaging (WSCSP), and a new wafer-scale-applied underfill technology called wafer pre-encapsulation. Using Technical Cost Modeling the paper tracks and examines the costs for the three implementations, starting from wafer-level through IC packaging to board placement. Manufacturing cost sensitivity is examined for a variety of manufacturing conditions and results are presented.
Chip-scale package
Wafer-scale integration
Wafer-level packaging
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Electronic Packaging
Integrated circuit packaging
Manufacturing cost
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Wafer-level packaging has become one of the semiconductor industry's most efficient packaging technologies due to its advantages in terms of size reduction and reliability improvement. In wafer-level packaging, unlike the traditional packaging technique, the silicon dies are encapsulated by epoxy molding compound first while at wafer-level before dicing into individual package. The package undergoes several high-temperature fabrication processes which may induce high stresses on the materials' interfaces. Interfacial failure is a common issue in semiconductor packages. Finite element analysis has become one of the most widely used approaches in analyzing potential interfacial failures in semiconductor packages. But for the wafer-level package, the molded wafer has a large diameter with very thin multiple components. Using conventional finite element modeling of the whole molded wafer may consume immense computational cost since it involves a large number of mesh elements to achieve reliable results. In this study, a global-to-local finite element modeling technique was carried out to evaluate the potential interfacial failure in a fan-out wafer-level package. The analysis was right after the post-mold curing of the glass wafer. The thermomechanical loads were applied to the glass wafer during global modeling. Then, using the imported solutions from the global model as boundary constraints, local modeling (or sub-modeling) was carried out to have a more detailed stress analysis and investigation of the critical region. The potential interfacial failure was assessed based on the available adhesion strength of the material. Moreover, the finite element model was validated through wafer warpage comparison to the existing experimental measurement using Shadow Moiré.
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MEMS devices are continuous evolving to achieve smaller size and lower cost with improved performance. The Through silicon via (TSV) technology offers a promising approach from the perspective of MEMS device packaging and integration. In this paper, we report our latest progress on wafer level packaging of MEMS devices by via-last process. The 200mm MEMS wafer was bonded with a glass cap wafer. Then, the vertical TSV structure with aspect ratio of 3:1 was realized from the device wafer side. The silicon vias are insulated by PECVD silicon dioxide. All the process steps are realized at the wafer level using the state-of-the-art facilities. The via-last integration, electrical test and reliability test are performed. The open/short electrical test results approve the principle, and the reliability test results further convince the developed via last process. This paper introduces a robust and cost-effective solution for heterogeneous 3D integration.
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As the market drives electronic products to be smaller and faster, designers must use advanced packaging technologies. In many cases, these technologies are significantly more expensive than traditional packaging, but are necessary to meet the product requirements. Both fan-out wafer level packaging and 2.5D packaging on a silicon interposer enable designers to package multiple die in close proximity. This close proximity helps achieve miniaturization and may enable better performance since die to die interconnect is shorter. However, care must be taken to manage the total cost and yield of the system. Both of these technologies have the potential to meet the smaller and faster market requirement, but if either is used on the wrong design, the cost can be high and the yield can be low. In this paper we will compare and contrast the packaging cost drivers for multi-die fan-out wafer level packaging and 2.5D packaging on a silicon interposer. Total cost and yield plus individual activity costs and yields will be presented across a range of design characteristics including package size, die size, number of die, and number of IOs. An in depth analysis of the cost of cumulative yield loss will be presented for both technologies. A sensitivity analysis on key cost and yield drivers will also be presented in the paper.
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Abstract A high I/O density and high performance wafer level packaging technology called the Compliant Wafer Level Package (CWLP) is reported. The necessity for compliant interconnects in upcoming generations of electronic products is discussed by analyzing the technology requirements projected by the International Technology Roadmap for Semiconductors (ITRS). To be a true wafer level package, the technology should have following three characteristics11: I) package all Integrated Circuits (ICs) intact on wafer at once, II) perform wafer level test and burn-in, and III) assemble the WLP on the system board without using an underfill. Compliant interconnects are essential to accomplishing wafer level test and assembly without underfill. These topics are discussed in the paper followed by fabrication and performance analysis of the CWLP technology.
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Wafer backgrinding
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There is growing demand for wafer level packaging, which enables thinner, lighter, and more cost effective packaging solutions. However, these demands come with a penalty; reduced package footprint limits the number of I/Os that can be realized in the smaller formfactor. In order to compensate this drawback, wafer level packaging fan-out has been drawing great attention, since fanning out of RDL beyond the die domain not only allows a higher number of I/Os without increasing the die size, but also allows to mount other passives or chips within the package. Compared to conventional packages, a significantly thinner formfactor is thereby achieved. Without a substrate, the wafer level packaging fan-out interacts directly with the Printed Circuit Board (PCB). Like conventional flip chip packages, which are designed and manufactured to mitigate chip package interaction risks, wafer level packaging fan-out needs to be designed and manufactured to mitigate chip board interaction risks. To address this challenge, a test vehicle was designed and manufactured based on silicon on insulator technology. Drop and temperature cycling test on board were performed on the assembled test vehicle. To understand the failure mechanisms, failure mode analysis and Weibull analysis were performed.
Wafer-level packaging
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Wafer-scale integration
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