Dual phase TOSI-gate process on High-K dielectrics in a CMP-less flow
A. MondotMarkus MüllerA. TalbotC. ViziozSimone PokrantF. LeverdF. MartínC. LerouxY. MorandS. DescombesD. AiméF. AllianP. BessonT. Skotnicki
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In this paper, we demonstrate for the first time a new original approach of the integration of dual phase totally silicided (TOSI) gates using a close-to-standard CMOS flow without any additional CMP step targeting the use of NiSi for NMOS and Ni 2 Si for the PMOS gate electrode on high-k dielectrics. The impact of the TOSI-process on the gate stack characteristics is investigated in detail on capacitance, gate leakage and work function data. With respect to poly-Si gated devices we find a significant reduction of the effective oxide thickness in inversion without degradation of the gate leakage statistics. The results emphasize the potential of the integration of TOSI-gates on high-k gate oxidesKeywords:
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Metal gate electrodes with two different work functions, /spl sim/4.5 and /spl sim/4.9 eV for NMOS and PMOS, respectively, were obtained by single-step full silicidation of poly gates. Reduction of polysilicon depletion was /spl sim/0.25 nm. Pile-up of arsenic at the NMOS dielectric is believed responsible for NiSi work function modification. Metal gate may offer little or no gate current reduction for the same T/sub oxinv/ as poly gate.
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An SPDT switch consisting of both nMOS and pMOS transistors is presented. Compared with conventional SPDT switches using only nMOS transistors under the same bias condition, the proposed switch exhibits better power-handling capability (PHC). The mechanism for the PHC improvement is explained. A prototype is implemented using a 0.18-um CMOS process. Measurement results show that, at 2.4 GHz, the insertion loss is 0.62 dB when the nMOS transistors are on and 0.91 dB when the pMOS transistors are on. For both modes, the measured return loss and isolation are better than 10 dB and 19 dB, respectively, up to 6 GHz. Under 1.8-V operation, the switch is able to handle a 26.1-dBm input power when the nMOS transistors are on and a 24.0-dBm input power when the pMOS transistors are on.
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We have successfully demonstrated very high-performance PMOS and NMOS transistors with high-K/metal-gate gate stacks with the right threshold voltages for both p- and n-channels on bulk Si. We believe that high-K/metal-gate is an option for the 45 nm high-performance logic technology node.
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