Effect of surface treatment on electromigration in sub-micron Cu damascene interconnects
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Electromigration
Copper interconnect
Chemical Mechanical Planarization
Diffusion barrier
Surface diffusion
Low-k dielectric
The chemical-mechanical global planarization mechanism to the common low-k dielectric material is analyzed.The effect of several factors including pressure,abrasive,pH and temperature in the chemical-mechanical polishing process of low-k dielectric material on the polishing rate and surface appearance are discussed.
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Low-k dielectric
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As device interconnects continue to scale, copper metallization and low dielectric constant materials will begin as soon as the 180 nm technology. The damascene approach with either CVD or PVD conformal coverage of good diffusion barrier layers, enhanced filling of Cu by CVD or electroplating as well as chemical-mechanical polishing of low-k material and Cu may be required to achieve high-level integration.
Copper interconnect
Chemical Mechanical Planarization
Diffusion barrier
Low-k dielectric
Barrier layer
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Electromigration
Copper interconnect
Chemical Mechanical Planarization
Diffusion barrier
Surface diffusion
Low-k dielectric
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A matrix of characterization techniques is presented, aiming at a thorough investigation of novel barrier / seed films with respect to their applicability in Cu damascene interconnects. The paper primarily focuses on the reliable testing of the Cu diffusion barrier performance using bias temperature stress (BTS) and triangular voltage sweep (TVS), as well as on the testing of Cu-wetting with regard to electromigration (EM), and on direct Cu plating. Typical test procedures are described. A good adhesion to low-k dielectrics, a good oxygen diffusion barrier performance and chemical mechanical polishing (CMP) capability are identified as further important criteria.
Electromigration
Copper interconnect
Diffusion barrier
Chemical Mechanical Planarization
Barrier layer
Characterization
Plating (geology)
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A significant improvement in electromigration performance for copper dual damascene structures was observed with the use of Pulsed Deposition Layer (PDL) TiN(Si) as a copper diffusion barrier layer instead of conventional sputtered (PVD) Ta/TaN. When an Ar sputter preclean was used, copper agglomeration occurred during the high temperature PDL process. An integration method was developed for the PDL film that avoids copper agglomeration on via sidewalls and has minimal barrier at the bottom of the via. The resulting process had lower via resistance, improved via stress migration and longer electromigration lifetime in multi-link testers than PVD Ta/TaN in both SiO/sub 2/ and PECVD SiOC low k dielectrics.
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Copper interconnect
Diffusion barrier
Barrier layer
Chemical Mechanical Planarization
Physical vapor deposition
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Electromigration
Copper interconnect
Low-k dielectric
Diffusion barrier
Chemical Mechanical Planarization
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The film properties of two PECVD deposited dielectric copper barrier films have been optimized to improve BEOL device reliability in terms of electromigration. Two critical aspects that affect electromigration are the dielectric barrier film hermeticity and adhesion to copper. We use a method to quantify the barrier film hermeticity of the BLO/spl kappa/ I low-/spl kappa/ dielectric film to be similar to that of silicon nitride. In addition, the interfaces between damascene nitride with copper, as well as BLO/spl kappa/ I with copper have been engineered to improve the interfacial adhesion energy to >10 J/m/sup 2/ for both damascene nitride and BLO/spl kappa/ I.
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Electromigration
Low-k dielectric
Chemical Mechanical Planarization
Barrier layer
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Electromigration testing pattern to identify the dominant diffusion path of Copper (Cu) damascene interconnects is proposed. It is confirmed that dominant diffusion path is the interface between Cu and barrier dielectrics using the proposed testing pattern. After identification of the dominant path, the effects of the plasma treatment and barrier dielectric SiC/sub x/N/sub y/ and SiC/sub x/ on the EM performance is investigated. Failure analysis reveals that Cu oxide at the interface of SiC/sub x/ samples with H/sub 2/ plasma treatment accelerates the Cu EM diffusion, resulting in lower activation energy and shorter lifetime. In addition, it is also found that nitrogen at the interface retards Cu diffusion drastically.
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Copper interconnect
Diffusion barrier
Low-k dielectric
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Application of Chemical-mechanical-polishing of the dielectric layer in multilevel metallization is introduced. To acheive globally planarized dielectric surfaces in severe topologies, some structures using mask and stop layer or double deposited dielectric layers for selective polishing are proposed. The characteristics of this polishing process were studied on wafer with real device topology. Experimental results were founded by measuring electrical characteristics and electromigration of metal lines and monitoring the cross-sectional view of planarized dielectric layer in the wafer.
Chemical Mechanical Planarization
Electromigration
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Electromigration
Copper interconnect
Low-k dielectric
Chemical Mechanical Planarization
Delamination
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