A statistical study of magnetic tunnel junctions for high-density spin torque transfer-MRAM (STT-MRAM)
R. S. BeachTai MinC. HorngQ. ChenPhillip ShermanSon LeSung Man YoungKongtan YangHao YuXianyang LuW. KulaTom ZhongRun XiaoAihua ZhongG. LiuJimmy J. KanJiahui YuanJ. ChenR. TongJun‐Chau ChienTerry TorngD.D. TangP. WangM. ChenS. AssefaMasood QaziJ. DeBrosseM. C. GaidisSivananda KanakasabapathyYuan LüJ. NowakE. J. O’SullivanT. MaffittJ. Z. SunW. J. Gallagher
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We have demonstrated a robust magnetic tunnel junction (MTJ) with a resistance-area product RA=8 Ω—μm 2 that simultaneously satisfies the statistical requirements of high tunneling magnetoresistance TMR ≫ 15σ(R Keywords:
Tunnel magnetoresistance
Magnetoresistive random-access memory
Spin-transfer torque
This letter presents energy-efficient MgO based magnetic tunnel junction (MTJ) bits for high-speed spin transfer torque magnetoresistive random access memory (STT-MRAM). We present experimental data illustrating the effect of device shape, area, and tunnel-barrier thickness of the MTJ on its switching voltage, thermal stability, and energy per write operation in the nanosecond switching regime. Finite-temperature micromagnetic simulations show that the write energy changes with operating temperature. The temperature sensitivity increases with increasing write pulsewidth and decreasing write voltage. We demonstrate STT-MRAM cells with switching energies of $<$
Magnetoresistive random-access memory
Tunnel magnetoresistance
Spin-transfer torque
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Magnetoresistive random-access memory
Spin-transfer torque
Tunnel magnetoresistance
Non-Volatile Memory
Racetrack memory
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We introduce a new device for reducing the switching current, Ic, in Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM). The Double Spin-torque Magnetic Tunnel Junction (DS-MTJ) uses spin torque from both top and bottom free-layer interfaces to reduce Ic by 2x. However, unlike previous work using Double Magnetic Tunnel Junctions (DMTJs), the DS-MTJ does not suffer from reduced magneto resistance (MR) due to increased series resistance. Experimental data using 10 ns write pulses demonstrates 2x reduction in Ic, and reliable writing down to an error-floor of write-error-rate (WER) = 1e-6.
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Programmability is as a severe challenge in development of spin-transfer torque magnetic random access memory (STT-MRAM). Theoretical analysis have indicated that nano-ring shaped magnetic tunneling junction (NR-MTJ) can achieve lower write current and higher write reliability compared to conventional elliptical-shaped MTJ (E-MTJ). In this work, we successfully patterned the NR-MTJ with 200nm outer diameter and 120nm inner diameter in commercial manufacturing facility, designed and fabricated a 4Kb STT-MRAM test chip with NR-MTJs. Testing results demonstrated successful read and write functionalities of our chip, and proved the theocratically-predicted electrical properties of NR-MTJs.
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In this report, we presented an NV Random Access Memory cell using a novel easy and proficient model of Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ). Magnetic tunnel junction (MTJ) devices are CMOS well suited with high steadiness, high dependability and non-volatility. The combination of magnetic tunnel junction with CMOS circuits in magnetic RAM (MRAM) or Magnetic FPGA can get the digital circuits to major advantages related with non-volatile facility like immediate on/off, Zero standby power use of goods and services. MTJ (Magnetic Tunnel Junction) devices have various advantages over other magneto-resistive devices for use in MRAM cells, like MRAM produces a big signal for the read operation and a varying resistance that can make the circuit. Due to these attributes, MTJ-MRAM can operate at high velocity. A completed simulation model for the 4T and 2MTJ SRAM design is shown in this report, which is grounded on the recently confirmed STT (Spin-Transfer Torque) writing technique which promises to take down the switching current losing to ~120μA and the STT RAM cache reduces total power consumption from 13.6μW -8.2μW. This model has been confirmed in Verilog A language and the whole work carried out and ran out on cadence virtuoso platform at 45nm.
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In this work we propose a magnetic random access memory (MRAM) bit-cell design based on non-local spin transfer torque (NLSTT). In the proposed bit-cell, the data is written into the free layer of a magnetic tunnel junction (MTJ) using spin diffusion current (non-local spin injection), without injecting charge current into the tunneling oxide. Thus, the reliability issues, related to dielectric breakdown due to high tunneling current density (for high switching speed) are significantly mitigated. Separation of read and write current paths in the bit-cell helps in optimizing read and write separately. Hence, higher MgO thickness can be used for higher cell TMR and higher read disturb margin. Higher MTJ resistance resulting from thicker MgO also lets us use voltage mode sensing, that achieves higher speed for read operation. In the proposed bit-cell, we employ two supplementary spin injectors with tilted axis anisotropy, in order to compensate for the comparatively lower efficiency for non-local spin injection. Analysis of the proposed NLSTT-MRAM bit-cell is done using a physics based simulation framework, benchmarked with experimental data for lateral spin valve (LSV). Apart from high reliability, the proposed bit-cell achieves 110% higher tunnel magneto resistance (TMR) and 4X higher read margin for I ns switching speed as compared to standard I-transistor-I MTJ (1-T I-R) STT -MRAM of similar area.
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We report switching performance of perpendicularly magnetized Spin-Transfer Torque MRAM (STT-MRAM) devices with double tunnel barriers and two reference layers. We show that stacks with double tunnel barriers improve the switching efficiency (Eb/Ic0) by 2x, when compared to similar stacks with a single tunnel barrier. Switching efficiency up to 10 kBT/uA was observed in single devices. A large operating window, Vbreakdown-Vc10ns ∼ 0.7 V was achieved for 40nm devices, compared to 0.2V in single tunnel barrier devices.
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This paper presents a review and future prospects for the tunnel magnetoresistance (TMR) effect in magnetic tunnel junction (MTJ) and spin manipulation technologies such as spin-transfer torque (STT) for magnetoresistive random access memory (MRAM). Major challenges for ultrahigh-density STT-MRAM with perpendicular magnetization and novel functional devices related to MRAM are discussed.
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Spin-torque transfer magnetoresistive random-access memory (STT-MRAM) is far more energy efficient than field MRAM. This chapter describes the memory operation and the performance of STT-MRAM. It discusses energy barriers as a function of a magnetic tunnel junction (MTJ) film stack and device structure. The chapter focuses on the switching properties. The discussion starts from a simple uniform magnetization reversal model, called the Macrospin model, in which the magnetization of the entire MTJ free layer magnetization is assumed to precess in unison under spin current. Then, the chapter discusses two STT-MRAM device reliability issues: tunnel barrier degradation and data retention. It covers an MgO tunnel barrier degradation model and the relation between the thermal energy barrier and the data retention time performance at the chip level. The chapter also discusses the 1 MTJ-1 transistor MRAM cell design and scaling. It covers the SPICE model for memory chip-level circuit simulation.
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Spin-transfer torque
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Perpendicular magnetic tunnel junctions (MTJ) are widely being researched as they are the key component in advanced spin transfer torque magnetic random access memory (STT-MRAM).
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