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    Low cost technology for high frequency bipolar integrated circuits
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    Abstract:
    A new low cost technology for high frequency bipolar circuits is proposed. It upgrades a classical "LISA" (Local Implantation Self Aligned) technology using a 14 masks process. The "basic" npn elementary transistor in the new technology has a 2.2 GHz cutoff frequency, and the parasitic elements in circuits are reduced. The performances of the new technology are verified by means of some demonstrator circuits: a "Gilbert" cell with a bandwidth of 700 MHz, and some broadband, high frequency amplifiers.
    Keywords:
    Cutoff frequency
    Integrated injection logic
    High-speed InGaP/GaAs heterojunction bipolar transistors (HBTs) with a small emitter area of 0.35 × 3.8 µm are described. A cutoff frequency fT of as high as 86 GHz and a maximum oscillation frequency fmax of as high as 120 GHz are achieved at a collector current of as low as 1 mA. The peak fT and the peak fmax are 121 and 149 GHz, respectively. These excellent characteristics are due to a heavily-doped thin base layer and reduced parasitic capacitance of the base-collector junction.
    Cutoff frequency
    Heterojunction bipolar transistor
    Heterostructure-emitter bipolar transistor
    Parasitic capacitance
    Oscillation (cell signaling)
    Diffusion capacitance
    Citations (4)
    A CMOS circuit element equivalent to a bipolar junction transistor (BJT) which provides symmetrical performances of npn/pnp and ideality factor programming is proposed. Simulation showed that the /spl beta/, and Early voltage are superior to those of a typical BJT below about 1.65 GHz in a 0.8 /spl mu/m CMOS technology and the fabricated prototype has 2.3/spl times/10/sup -16/ A of I/sub S/, 2.4 mA of I/sub KF/ and 390 V of Early voltage.
    Integrated injection logic
    A pseudo-HBT (heterojunction bipolar transistor) having a cutoff frequency (f/sub T/) twice as high as that of a conventional bipolar transistor at 87 K is demonstrated. This is the first bipolar transistor that has a higher f/sub T/ below 100 K than at room temperature. The low-impurity-concentration graft base reduces the electron injection into the graft base, resulting in a high cutoff frequency. The impurity concentration of the graft base (extrinsic base) must be kept lower than that of the intrinsic base. In addition. the base profile must be kept as abrupt as possible to prevent the reduction of effective bandgap narrowing in the base.< >
    Heterojunction bipolar transistor
    Cutoff frequency
    Base (topology)
    Cut-off
    Heterostructure-emitter bipolar transistor
    Citations (0)
    The purpose of this thesis is to establish a design rule with which the bipolar transistors at any specific temperature can be attained. Firstly, the working characteristics of silicon bipolar transistors at low temperature are analyzed and discussed. The physical models of current gain and cutoff frequency fit in with any specific temperature are established. These offer the necessary physical basis to suggest the temperature-scaling law. On the basis of low temperature effects of bipolar transistor, the changing condition of the doping concentration in the emitter and base and the width of the emitter and base are emphatically analyzed. The integrated program to get temperature - scaling factors is presented. The optimized results of current gain and cutoff frequency at any specific temperature according to the temperature scaling law are studied.
    Cutoff frequency
    Cut-off
    Operating temperature
    Heterostructure-emitter bipolar transistor
    Citations (0)
    High performance Pnp AlGaAs/InGaAs heterojunction bipolar transistors (HBTs) have been fabricated. The transistors have a 300 Å strained InGaAs base, with indium composition linearly graded from 0 to 15%. The cutoff frequency and maximum oscillation frequency for a transistor with emitter area of 2 × 8 μm2 are measured to be 23.3 GHz and 40 GHz, respectively, at a collector current of −10 mA. These are the highest published results for Pnp HBTs.
    Heterojunction bipolar transistor
    Cutoff frequency
    Heterostructure-emitter bipolar transistor
    Indium gallium arsenide
    Oscillation (cell signaling)
    Base (topology)
    Citations (8)
    In this work, the design of double heterojunction bipolar transistors (DHBTs) is to improve the unit current gain cutoff frequency (fT). We proposed using a compositionally graded emitter and adding a ledge layer between the base and the emitter to enhance fT. These results exhibit the high fT of these DHBTs.
    Cutoff frequency
    Heterojunction bipolar transistor
    Heterostructure-emitter bipolar transistor
    Presented are the results of a merged CMOS/bipolar process used to implement circuit structures using both fully isolated bipolar transistors with low collector series resistance and CMOS transistors. Latch-up suppression and effective bipolar performance are simultaneously achieved by the combined use of an n+ buried layer, epitaxial processing and a tailored base ion implant. A merged CMOS/bipolar buffer circuit is described and measured results are shown.
    Integrated injection logic
    Heterostructure-emitter bipolar transistor
    Citations (21)
    A model has been developed which generates the high-frequency ic − vce output characteristics of bipolar transistors from computed cutoff frequency against current density data. The presented results, which can be used directly for large-signal modelling, are the first report of high-frequency output characteristics of bipolar transistors.
    Cutoff frequency
    Heterostructure-emitter bipolar transistor
    Heterojunction bipolar transistor
    Current injection technique
    SIGNAL (programming language)
    Citations (5)
    Calculating the cutoff frequency fT of bipolar transistors from the emitter-to-collector delay neglects the heavy influence of parasitic reactances on the frequency response of realistic transistors. A more complete equivalent circuit modelling reveals that the speed advantage of Npn against Pnp heterojunction bipolar transistors of common geometry, base width, and doping profile decreases as the transistor is scaled up in size. For power applications, the fT of InP/GaInAs Pnp devices may even surpass that of Npn transistors.
    Cutoff frequency
    Heterojunction bipolar transistor
    Heterostructure-emitter bipolar transistor
    Citations (3)