Cell Signal Distribution Characteristics For High Density FeRAM

The sub-bitline (SBL) sensing voltage of a cell and total cell array can be measured by the method of SBL voltage evaluation method. The VlOSAID tester can collect all SBL signals. The hierarchical bitline of unit cell array block is composed of the cell array of 2k rows and 128 columns, which is divided into 32 cell array sections. The unit cell arras section is composed of the cell array of 64 rows and 128 columns. The average sensing voltage with 2Pr value of 5uC/cm² and SBL capacitance of 40fF is about 700m V at 3.0V operation voltage. That is high compensation method for capacitor ZPr degradation effect. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about Ie" than 5uC/cm² Index-ferroelectric memory, boost voltage control, hierarchical bitline, SBL, MBL