Ferroelectric RAM

Ferroelectric RAM (FeRAM, F-RAM or FRAM) is a random-access memory similar in construction to DRAM but using a ferroelectric layer instead of a dielectric layer to achieve non-volatility. FeRAM is one of a growing number of alternative non-volatile random-access memory technologies that offer the same functionality as flash memory. Ferroelectric RAM (FeRAM, F-RAM or FRAM) is a random-access memory similar in construction to DRAM but using a ferroelectric layer instead of a dielectric layer to achieve non-volatility. FeRAM is one of a growing number of alternative non-volatile random-access memory technologies that offer the same functionality as flash memory. FeRAM's advantages over Flash include: lower power usage, faster write performance and a much greater maximum read/write endurance (about 1010 to 1014 cycles). FeRAMs have data retention times of more than 10 years at +85 °C (up to many decades at lower temperatures).Market disadvantages of FeRAM are much lower storage densities than flash devices, storage capacity limitations and higher cost. Like DRAM, FeRAM read process is destructive, necessitating a write-after-read architecture. Ferroelectric RAM was proposed by MIT graduate student Dudley Allen Buck in his master's thesis, Ferroelectrics for Digital Information Storage and Switching, published in 1952. In 1955 Bell Telephone Laboratories was experimenting with ferroelectric-crystal memories. Development of FeRAM began in the late 1980s. Work was done in 1991 at NASA's Jet Propulsion Laboratory on improving methods of read out, including a novel method of non-destructive readout using pulses of UV radiation. In 1998, Hyundai Electronics (now SK Hynix) developed FeRAM technology for commercial production. A major modern FeRAM manufacturer is Ramtron, a fabless semiconductor company. One major licensee is Fujitsu, who operates what is probably the largest semiconductor foundry production line with FeRAM capability. Since 1999 they have been using this line to produce standalone FeRAMs, as well as specialized chips (e.g. chips for smart cards) with embedded FeRAMs. Fujitsu produced devices for Ramtron until 2010. Since 2010 Ramtron's fabricators have been TI (Texas Instruments) and IBM. Since at least 2001 Texas Instruments has collaborated with Ramtron to develop FeRAM test chips in a modified 130 nm process. In the fall of 2005, Ramtron reported that they were evaluating prototype samples of an 8-megabit FeRAM manufactured using Texas Instruments' FeRAM process. Fujitsu and Seiko-Epson were in 2005 collaborating in the development of a 180 nm FeRAM process. In 2012 Ramtron was acquired by Cypress Semiconductor.FeRAM research projects have also been reported at Samsung, Matsushita, Oki, Toshiba, Infineon, Hynix, Symetrix, Cambridge University, University of Toronto, and the Interuniversity Microelectronics Centre (IMEC, Belgium). Conventional DRAM consists of a grid of small capacitors and their associated wiring and signaling transistors. Each storage element, a cell, consists of one capacitor and one transistor, a so-called '1T-1C' device. DRAM cells scale directly with the size of the semiconductor fabrication process being used to make it. For instance, on the 90 nm process used by most memory providers to make DDR2 DRAM, the cell size is 0.22 μm², which includes the capacitor, transistor, wiring, and some amount of 'blank space' between the various parts — it appears 35% utilization is typical, leaving 65% of the space empty (for separation). DRAM data is stored as the presence or lack of an electrical charge in the capacitor, with the lack of charge in general representing '0'. Writing is accomplished by activating the associated control transistor, draining the cell to write a '0', or sending current into it from a supply line if the new value should be '1'. Reading is similar in nature; the transistor is again activated, draining the charge to a sense amplifier. If a pulse of charge is noticed in the amplifier, the cell held a charge and thus reads '1'; the lack of such a pulse indicates a '0'. Note that this process is destructive, once the cell has been read. If it did hold a '1,' it must be re-charged to that value again. Since a cell loses its charge after some time due to leak currents, it must be actively refreshed at intervals. The 1T-1C storage cell design in an FeRAM is similar in construction to the storage cell in widely used DRAM in that both cell types include one capacitor and one access transistor. In a DRAM cell capacitor, a linear dielectric is used, whereas in an FeRAM cell capacitor the dielectric structure includes ferroelectric material, typically lead zirconate titanate (PZT). A ferroelectric material has a nonlinear relationship between the applied electric field and the apparent stored charge. Specifically, the ferroelectric characteristic has the form of a hysteresis loop, which is very similar in shape to the hysteresis loop of ferromagnetic materials. The dielectric constant of a ferroelectric is typically much higher than that of a linear dielectric because of the effects of semi-permanent electric dipoles formed in the crystal structure of the ferroelectric material. When an external electric field is applied across a dielectric, the dipoles tend to align themselves with the field direction, produced by small shifts in the positions of atoms and shifts in the distributions of electronic charge in the crystal structure. After the charge is removed, the dipoles retain their polarization state. Binary '0's and '1's are stored as one of two possible electric polarizations in each data storage cell. For example, in the figure a '1' is encoded using the negative remnant polarization '-Pr', and a '0' is encoded using the positive remnant polarization '+Pr'. In terms of operation, FeRAM is similar to DRAM. Writing is accomplished by applying a field across the ferroelectric layer by charging the plates on either side of it, forcing the atoms inside into the 'up' or 'down' orientation (depending on the polarity of the charge), thereby storing a '1' or '0'. Reading, however, is somewhat different than in DRAM. The transistor forces the cell into a particular state, say '0'. If the cell already held a '0', nothing will happen in the output lines. If the cell held a '1', the re-orientation of the atoms in the film will cause a brief pulse of current in the output as they push electrons out of the metal on the 'down' side. The presence of this pulse means the cell held a '1'. Since this process overwrites the cell, reading FeRAM is a destructive process, and requires the cell to be re-written if it was changed.