Fan-Out Wafer Level Packaging Development Line

With the slowing down of Moore's law, the semiconductor industry is increasingly looking to advanced packaging for achieving system scaling at packaging level. Across the industry, in high volume factories that support assembly and packaging of semiconductor ICs, fabless companies, foundries, equipment and materials developers, increased constraints are seen in terms of allocating resources for research and development of advanced packaging technologies and solutions to meet market requirements. IME has worked with multiple industry partners to establish a FOWLP development Line to address these challenges to build broad advanced-packaging platforms to enable product and technology pathfinding for industry applications such as mobility, 5G, mmWave, Data Centre and automotive requirements This paper will provide an overview of the FOWLP development line, review of mold 1st and RDL 1st FOWLP technologies with multi-layer 2um line and spacing, RDL process and integration on 300mm wafer. The example of few novel packaging approaches such as large size RDL molded interposer with and without embedded fine interconnect chip, 3D integrated package-on-package, and the 2-layer molded antenna-in-package will be described.