Impact of Bottom Electrode Roughness on the Analog Switching Characteristics in Nanoscale RRAM Array

Computing-in-memory (CIM) architecture based on emerging resistive switching memories shows great potential to build energy-efficient hardware for artificial intelligence applications. For resistive random-access memory (RRAM), the bottom electrode (BE) roughness has been shown to impact the electrical characteristics [1] – [3] . However, previous works mainly focus on the effect of BE roughness on forming in single or a few RRAM devices with relatively large size (~μm) [1] – [3] . In this work, we study the impact of BE roughness in arrays of nanoscale RRAM with sizes down to 50 nm (applicable for 28nm technology BEOL), including retention, variation, and analog switching characteristics.