Buffer Reduction via N-Phase Clocking in Adiabatic Quantum-Flux-Parametron Benchmark Circuits

Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family capable of producing extremely low-energy computing systems. However, AQFP circuits have some challenges to overcome before it can go into practical use and improving circuit integration is one of them. Conventionally, a 4-phase clocking distribution has been utilized as the power-clock network for AQFP circuits. This method requires gates to transmit data signal currents on adjacent phases. The drawback to 4-phase clocking is not only the large latency due to limiting signal propagation to 4-stages of logic in a single cycle, but also the enormous amount of signal buffering that is required for large circuits. Buffering uses up valuable area on the chip. We propose the adoption of an n-phase clocking method to not only reduce the latency of AQFP circuits but to also reduce the number of buffers, particularly for n larger than 4. When the number of phases per clock cycle increases by x times, we show that the number of buffers can be decreased to 1/x times in a number of AQFP benchmark circuits.