Sum-Addressed-Memory (SAM) decoder realization in delayed-reset logic with 242ps latency

As the frequency of operation of microprocessor systems such as UltraSparc is soaring up over a Gigahertz, clock period to less than 1.0 nanosec, it is extremely important for the circuits to be keeping up in speed when every picosecond counts. To achieve so high frequency of operation, design of faster gates with delays of less than lOOps becomes necessary. Different styles of CMOS dynamic circuits have been used to realize simple to complex logic while consuming low power, less area and yet achieve high speed for a given technology. Precharge logic, domino logic, delayed-reset logic and self-resetting logic each have their own advantages and disadvantages. In this paper the implementation of an ADDer followed by Decoder, combined with SAM, Sum-Address-Memory concept [1,2,3,4] is shown to be achieved in two complex delayed-reset logic gates with the latency 240ps (at typical 0.25u process and worse case condition of low operating voltage and high temperature), equivalent to 2 three input NAND gate delay.