Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices

We present an advanced CMOS integration scheme based on embedded SiGe (eSiGe) with a novel graded germanium process. The retention of channel strain enabled a pFET performance gain of 15% over a non-graded eSiGe control. When combined with a compressive stress liner (CSL), the pFET drive current reached 770muA/mum at I off = 100nA/mum with V DD = 1V. Competitive nFET performance was maintained. Parasitics such as silicide and junction characteristics were not degraded