An equivalent circuit model for simulation of the ggNMOS transient triggering under ESD operating conditions

A new equivalent circuit suitable for transient simulation methodology of Gate-Grounded NMOS transistor (ggNMOS) used in Electrostatic Discharge (ESD) protection circuits is proposed in this paper. The target technology is a classical CMOS 0.25 μm. This model, contrary to classical I-V static model, is intended to cover the dynamic comportment of the ggNMOS during all the phases of the Transmission Line Pulse (TLP) stress tests. Starting from experimental TLP measures concerning the transient ggNMOS triggering, it is demonstrated that the modeling can be based on a classical equivalent circuit. The parameters extraction methodology for the model, relied to the physical structure of the component is also presented. Finally, simulation results are presented and compared with experimental data. The model is then correlated to the simplified physical structure of the device. By example for a ggNMOS W/L=3D50μm/0.5μm the transient characteristics for TLP current of 0.3 and 0.7A created by simulating the model are the same as the one measured on the TLP tester thus validating the model.