Linearity Performance Analysis of Double Gate (DG) VTFET Using HDB for RF Applications

In recent low-power electronics industry, Tunnel field-effect transistors (TFETs) have shown the superior performance such as decreased leakage current and lower subthreshold slope (SS). Previously available research work have recognized the fact that the precise evaluation of linearity is critical in short channel devices. The linearity analysis of double gate vertical TFET using hetero-dielectric buried oxide (HDB) for high-frequency applications has been investigated in this paper. The aim of using double gate (DG), HDB and work-function engineering is to improve the linearity performance. This work comprises of the analysis of the linearity figure-of-merits in terms of third-order transconductance (gm3), VIP2, VIP3, IMD3, IIP3 and 1-dB compression point.