Evaluation of Q/sub bd/ for electrons tunneling from the Si/SiO/sub 2/ interface compared to electron tunneling from the poly-Si/SiO/sub 2/ interface

Electrical time-to-breakdown (TTB) measurements have shown the charge to breakdown Q/sub bd/ of gate oxide capacitors fabricated on n-type well (n-well) substrates always to be higher than that of capacitors on p-type well (p-well) substrates on the same wafer when both are biased into accumulation under normal test conditions. Here the authors correlate the higher n-well Q/sub bd/ to smooth capacitor oxide/substrate interfaces and minimized grain boundary cusps at the poly-Si gate/oxide interfaces, confirming that Fowler-Nordheim tunneling is the dominant current conduction mechanisms through the oxide. They correlate higher Q/sub bd/ to higher barrier height for a given substrate type and observe that the slope of the barrier height versus temperature plot is lower for both p-well and n-well cases with electrons tunneling from the silicon substrate. This is attributed to surface roughness at the poly-Si gate/SiO/sub 2/ interface. A poly-Si gate deposition and annealing process with clean, smooth oxide/substrate interfaces will improve the p-well breakdown characteristics and allow higher Q/sub bd/ to be achieved. >