Silicon Quality Versus Thickness For Novel Silicon On Boron Phosphide Soi Process

Results are reported for a single temperature Si-BP-Si process which utilizes 0.2 and 0.4 μm of high resistivity BP covered by a single 1–5 μm silicon epitaxial layer on which PMOS devices were fabricated. Transistor and capacitor measurements were used to characterize the quality of the silicon films. Impurity concentrations on 1.0 and 2.0 μm silicon layers were as high as 3×10 17 cm −3 due to auto doping from the BP layer. MOS transistors manufactured on these layers did not work properly. Device characteristics improved on thicker silicon layers. The impurity concentration was as low as 10 15 cm −3 on the 5.0 μm silicon layers. Surface state densities were found to be as low as 5×10 11 eV −1 cm −2 with subthreshold currents as low as 10 −11 amperes. On all wafers the subthreshold slope varied from 90 to 100 mV/decith little variation due to silicon thickness. Linear and saturation mobilities were process limited with values on the 5.0 μm layers as high as 250 and 160 cm 2 /V-s respectively. Characteristics of devices fabricated on 5 μm silicon layers were comparable to those of devices fabricated on bulk silicon processed at the same time indicating high quality silicon growth.