LORES - Logic Reorganization System

Shunichiro Nakamura,Shinichi Murai,Chiyoji Tanaka,Masayuki Terai,Hideo Fujiwara,Kozo Kinoshita

LORES - Logic Reorganization System

1978

Shunichiro Nakamura
Shinichi Murai
Chiyoji Tanaka
Masayuki Terai
Hideo Fujiwara
Kozo Kinoshita

Described is the outline and the experimental results of the system which automatically restructures and partitions a logic circuit consisting of standard SSI's and MSI's so that the gate types and the numbers of input/output terminals of the reorganized circuits are within the restrictions of the specified LSI.

Keywords:

Real-time computing
Diode–transistor logic
Sequential logic
Computer architecture
Logic family
Logic gate
Resistor–transistor logic
Logic optimization
Electronic engineering
Three-state logic
Pass transistor logic
Computer science
Programmable logic array
Programmable logic device

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