Effect of deposition temperature on electrical properties of one-transistor-one-capacitor (1T1C) FeRAM devices

This work investigates the effect of process temperature on one-transistor-one-capacitor ferroelectric random access memory (1T1C FeRAM) cells fabricated with a HfZrOx ultrathin film applied as the 1T1C capacitor. Traditionally, the capacitor in 1T1C devices is grown on the drain, and such a structure is a type of dynamic memory. Such a structure, however, is prone to the leakage current phenomenon, which causes the amount of charge stored in the capacitor to be insufficient, leading to inaccurate data reading. To solve this problem, an alternative 1T1C structure placing the capacitor on the gate terminal has been proposed. For these alternative 1T1C FeRAM devices, our experimental results indicate that the deposition temperature of the ferroelectric layer has a significant effect on the basic electrical properties. To clarify this phenomenon, we propose a physical model which is based on the effect of the deposition temperature on the HfZrOx grain size.