Investigation of Mobility Enhancement Effect in Process-Induced Strained Ultrathin Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors

Mobility enhancement effects in process-induced strained silicon-on-insulator (SOI) n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) are investigated using a combination of devices with different gate lengths. This method is useful for devices with short channels since it is free from the influence of pocket doping or parasitic resistance on the channel current. This approach is also useful to confirm the influence of variations in device parameters such as gate oxide thickness or SOI thickness. Using this method, large electron mobility enhancements in ultrathin (~12 nm) SOI devices with a stressed contact etch stop layer (CESL) are confirmed for a wide range of gate voltages. Furthermore, it is demonstrated that the CESL also increases the back-channel mobility.