A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization

At high conversion speed, time interleaving provides a viable way of achieving analog-to-digital conversion with low power consumption, especially when combined with the successive-approximation-register (SAR) architecture that is known to scale well in CMOS technology. In this work, we showcase a digital background-equalization technique to treat the path-mismatch problem as well as individual ADC nonlinearities in time-interleaved SAR ADC arrays. This approach was first introduced to calibrate the linearity errors in pipelined ADCs [1], and subsequently extended to treat SAR ADCs [2]. In this prototype, we demonstrate the effectiveness of this technique in a compact SAR ADC array, which achieves 7.5 ENOB and a 65dB SFDR at 600MS/s while dissipating 23.6mW excluding the on-chip DLL, and exhibiting one of the best conversion FOMs among ADCs with similar sample rates and resolutions [3].