ESD-failure of E-mode GaN HEMTs: Role of device geometry and charge trapping

Abstract We investigate the robustness of E-mode GaN HEMTs under ESD testing; specifically, we focus on three aspects, i.e. the impact of gate bias on TLP failure voltage, the role of device geometry (with focus on gate length), and the difference in failure voltage when tests are carried out under UV illumination. The results demonstrate that: (i) when the transistors are tested in semi-on and on-state (4 V