Deep trench SOI LIGBT with enhanced safe operating area

A novel deep trench SOI LIGBT with enhanced safe operating area has been proposed. Deep trench gate electrode, reaching buried oxide layer, has been directly introduced for achieving low on-resistance. Heavily doped p + region at the emitter side, which sandwiches between the n-drift region and n + emitter region, is provided as holes bypassing path for ensuring enhanced forward biased safe operating area. Some of holes will flow from the n-drift to the p + emitter without flowing through the pwell layer directly. On the other hand, the portion of the n-drift region which underlies the pwell is fully depleted at a relatively low voltage, thus preventing the voltage across the trench gate oxide from becoming too high and causing less reliable and stable problems. This JFET pinch-off effect keeps any hot-carrier injection (HCI) away from the sensitive gate oxide, providing HCI performance far superior to conventional LIGBT devices.