Effect of substrate temperature on sidewall erosion in high-aspect-ratio Si hole etching employing HBr/SF6/O2 plasma

A Si deep-trench etching process using HBr/SF6/O2 plasma was studied. It was found that when the hole trench width was decreased from 190 to 140 nm, erosions at the topmost part of the Si hole sidewall were observed at an incidence of 10 ppm, which was checked from top-down views of 928 million hole shapes per wafer. It was confirmed that when the cathode temperature was increased to 140 °C, no Si erosion occurred. It was found that etching at a higher temperature reduced the halogen content in the film deposited on the sidewall, making the film more protective, and suppressed Si erosion.