Simulation-based Verification of the Youngest-First Round-Robin Core Gating Pattern

Integrated circuit aging becomes a major concern with technology downscaling. Long-life systems therefore require better mechanisms for improving their lifetime. Here we present an implementation of the Youngest-First Round-Robin (YFRR) core gating pattern as a mean for reduction of aging in a four core multiprocessor. The pattern is optimal in respect to achieving the maximal possible system lifetime and significantly outperforms the simple Round-Robin (RR) pattern. For the purposes of simulation, a Verilog model of the circuit aging is developed and integrated in the "all-digital" simulation environment. The relative wear-out of the cores is obtained by using aging monitors which direct the core selection process of the YFRR pattern. The results confirm that YFRR excels when the initial age of the cores is uneven. Even greater than 32% increase in lifetime is obtained, predicted by the theoretical model which is based on a Weibul distribution of the lifetime reliability function. Here, we further find out that YFRR is far better than RR when the aging rate is high.