Novel Fine-Grain Back-Bias Assist Techniques for 3D-Monolithic 14nm FDSOI Top-Tier SRAMs

Abstract For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty, as well as the capability to route two additional row-wise signals on individual back planes. Experimental data are extracted from a 14nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078µm2 SRAM cell in order to properly model 3D top-tier cells. BTI measurements are done to ensure that the proposed assist do not provide additional stress. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/50% read/write access time improvement at VDD=0.8V and a reduction of minimum operating voltage Vmin by 60mV (up to 92mV with speed penalty) at 6σ w.r.t. planar SRAMs.